Browse Prior Art Database

VRAM/DRAM Memory Module

IP.com Disclosure Number: IPCOM000108459D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Beattie, I: AUTHOR [+3]

Abstract

Disclosed is a method of packaging DRAM and VRAM for graphics applications that significantly reduces pin count and wiring complexity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

VRAM/DRAM Memory Module

       Disclosed is a method of packaging DRAM and VRAM for
graphics applications that significantly reduces pin count and wiring
complexity.

      In graphics systems both VRAM (Video Random Access Memory) and
DRAM (Dynamic Random Access Memory) are often used.  VRAM is used for
the frame buffers to be displayed, and DRAM is used for additional
control or calculation planes, and for Z-buffers.  Currently, with
the majority of the logic highly integrated and packaged in very
large chips, minimizing pin count is critical for efficient
packaging.

      In this disclosure, an equal number of VRAM and DRAM modules
share common data and address buses.  Separate control lines are used
to select either VRAM or DRAM.  A block diagram that illustrates an
example of this connection is contained in the figure.  This is a
typical configuration for a graphics adapter containing both VRAM for
screen refresh and DRAM for off screen memory.

      The VRAM and DRAM modules may either be packaged together in a
single module or chip, or standard VRAM and DRAM modules could be
packaged on a small card.  This card can, in turn, either be soldered
or plugged in the main card.  If one assumes 256K by 4 memory
configuration, the pin savings of putting both the VRAM function and
DRAM function in a single chip is 17 (4 data and 9 address lines).
If five 256K by 4 standard DRAM modules five 256K by 4 standard VRAM
modules are packaged on card, the pi...