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Browse Prior Art Database

Fast Micro Channel Cache Control Lookup

IP.com Disclosure Number: IPCOM000108470D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

The IBM RISC System/6000* (RS/6000) contains an I/O Channel Controller (IOCC) which generates the MICRO CHANNEL* bus. The IOCC contains a pool of sixteen, 64-byte DMA buffers/control to provide a robust channel to/from system memory and the MICRO CHANNEL. When a Bus Master arbitrates for the bus, the four bit arbitration tag determines which one of the 16-Channel Status Registers (CSR) is to be used by the IOCC. A four-bit buffer field in the CSR determines which of the 16 DMA buffers/control is to be used for the transfer. Typically most memory slave channels insert wait states at the beginning of a transfer in order to perform I/O Architecture-specific background operations. This, however, reduces bus bandwidth and system performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 88% of the total text.

Fast Micro Channel Cache Control Lookup

       The IBM RISC System/6000* (RS/6000) contains an I/O
Channel Controller (IOCC) which generates the MICRO CHANNEL* bus.
The IOCC contains a pool of sixteen, 64-byte DMA buffers/control to
provide a robust channel to/from system memory and the MICRO CHANNEL.
When a Bus Master arbitrates for the bus, the four bit arbitration
tag determines which one of the 16-Channel Status Registers (CSR) is
to be used by the IOCC.  A four-bit buffer field in the CSR
determines which of the 16 DMA buffers/control is to be used for the
transfer.  Typically most memory slave channels insert wait states at
the beginning of a transfer in order to perform I/O
Architecture-specific background operations.  This, however, reduces
bus bandwidth and system performance.  The RS/6000's IOCC performed a
fast Cache Control lookup by:
      1) Transparently latching the arbitration tags with ARB/-GNT =
1.
      2) Utilizing custom Register Files to provide 2 fast lookups.
      3) Using transparent latches at the output of each register
file for combinatorial lookup and testability.
      4) Overlapping the Micro Channel arbitration with both lookups.
      5) Taking the outputs of the control lookup into the last
combinational terms with -S0,1 for the system memory slave CD READY
terms.

      With the above speed-ups, the IOCC system memory slave was able
to not insert wait states to the bus masters for the Cache Control
l...