Browse Prior Art Database

Sub-block Cache with Demand Sub-block Reloading in Conjunction with a RISC System

IP.com Disclosure Number: IPCOM000108475D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+3]

Abstract

The processor utilizes three mechanisms in the cache/memory subsystem in order to help improve system memory performance. These are cache line sub-block design, dynamic reloading of a cache line and early-outting a cache line reload. Cache Line Sub-blocks

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Sub-block Cache with Demand Sub-block Reloading in Conjunction with a RISC System

       The processor utilizes three mechanisms in the
cache/memory subsystem in order to help improve system memory
performance.  These are cache line sub-block design, dynamic
reloading of a cache line and early-outting a cache line reload.
Cache Line Sub-blocks

      Sub-block cache line design divides a 64-byte cache line into
four, 16-byte entities.  Each of these entities is referred to as a
sub-block.  A cache line is comprised of four sub-blocks.  Within the
cache tag directory, each sub-block has its own valid bit.  These
four valid bits are grouped together and comprise a quad word, or
sub-block, mask.  These valid bits are used to determine whether a
sub-block is valid when a request hits in the cache.  Therefore, a
sub-block is the smallest entity that can be placed into the cache
and validated.
Dynamic Reloading

      Dynamic reloading is a term used to describe a feature in the
processor memory queue logic.  This feature will dynamically continue
to load a cache line into the processor as long as a high priority
request is not waiting to be processed in the memory queue.  If a
high priority request is in the memory queue waiting to be processed,
the memory queue will "early out" the reload operation to perform the
high priority request.  Early out will be discussed later.
Description of Invention

      When the processor memory queue receives a cacheable load
request, it also receives a quad word mask indicating which
sub-blocks, if any, are already valid in the cache. The memory queue
logic will load the requ...