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Algorithm to Provide Imaginary Linear Addressing to Standard Buffers

IP.com Disclosure Number: IPCOM000108477D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR

Abstract

The I/O Channel Controller (IOCC) of the IBM RISC System/6000* (RS/ 6000) is capable of executing Programmable Input/Output (PIO) string operations from the central processor. The PIO data is sent and received by the processor over a system bus. This data, however, is not aligned with respect to the PIO address. Instead, it is simply left justified on the system bus. This is because the processor architecture defines the starting data of a PIO string operation to begin left justified in the appropriate General-Purpose Register (GPR). This way the processor simply sends/receives data to/from the GPRs over the system bus without any data muxing. The IOCC, however, must be capable of sending/receiving this data over the system bus and, in turn, align the data with respect to the PIO address on the MICRO CHANNEL*.

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This is the abbreviated version, containing approximately 52% of the total text.

Algorithm to Provide Imaginary Linear Addressing to Standard Buffers

       The I/O Channel Controller (IOCC) of the IBM RISC
System/6000* (RS/ 6000) is capable of executing Programmable
Input/Output (PIO) string operations from the central processor.  The
PIO data is sent and received by the processor over a system bus.
This data, however, is not aligned with  respect to the PIO address.
Instead, it is simply left justified on the system bus.  This is
because the processor architecture defines the starting data of a PIO
string operation to begin left justified in the appropriate
General-Purpose Register (GPR).  This way the processor simply
sends/receives data to/from the GPRs over the system bus without any
data muxing.  The IOCC, however, must be capable of sending/receiving
this data over the system bus and, in turn, align the data with
respect to the PIO address on the MICRO CHANNEL*.  This can be
accomplished by adding some barrel rotate muxes between the system
bus and the IOCC's PIO buffers and adding control logic to
align/unalign the data to/from the system bus.  However, this adds
more delay and control logic to the most critical paths within the
IOCC.  Another way would be to simply perform 1-byte transfers on the
MICRO CHANNEL, for all unaligned PIO string operations.  However,
this significantly degrades graphics performance (since most graphics
applications perform unaligned PIO strings).  The most obvious
approach would be to have a quad ported (two-read, two-write) PIO
buffer.  This, howeve...