Browse Prior Art Database

Micro Channel Streaming Data Acknowledgment Terms for Slaves

IP.com Disclosure Number: IPCOM000108480D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

This article discloses implementations for a Streaming Data slave for generating various signals for internal control. This allows these slaves to support Streaming Data transfers simply with minimal hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Micro Channel Streaming Data Acknowledgment Terms for Slaves

       This article discloses implementations for a Streaming
Data slave for generating various signals for internal control. This
allows these slaves to support Streaming Data transfers simply with
minimal hardware.

      Basic Transfer cycles on the MICRO CHANNEL* bus contain early
information from the master (e.g., 'TR 32', '-SBHE', 'BE(0-3)',
'M/IO', etc.) to allow the slave to easily determine the type of
transfer.  This allows slaves to determine the action required prior
to '-CMD' falling. '-CMD' is then used only to transfer data.  For
Streaming Data slaves information regarding the transfer from the
master is valid later during '-CMD' active.  This requires
implementing additional logic.

      The logic from Basic Transfer cycle is used by generating
internal streaming data acknowledgment terms that make the Streaming
Data cycle look like a compressed Basic Transfer data cycle.  This
implementation exhibits excellent MICRO CHANNEL timing
characteristics and provides a high degree of fault tolerance and
testability.

      Fig. 1 shows the generation of the signals 'SD_ACK1',
'SD_ACK2', 'SD_ACK3', '-ADD_CLK' and '-ICMD'.  Fig. 2 shows the
timing relationship between these internal signals and MICRO CHANNEL
signals.  In Fig. 3, 'A_ERROR' is address related error and 'D_ERROR'
is data parity error.  When 'SD_ACK1' is set, it indicates that both
master and slave are currently transfe...