Browse Prior Art Database

Parallel Mask Image Processor

IP.com Disclosure Number: IPCOM000108491D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kobayashi, Y: AUTHOR

Abstract

Disclosed is a system that processes binary two-dimensional images by using multiple 3x3 masks with pipeline operations. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

Parallel Mask Image Processor

       Disclosed is a system that processes binary
two-dimensional images by using multiple 3x3 masks with pipeline
operations.

                            (Image Omitted)

      A parallel mask image processor is a hardware device for fast
image processing using 3x3 masks.

      Raw binary image data are stored in image buffer 1 shown in the
figure.  These data are transferred to line buffer 2 by an N-bit
boundary; N is typically 16 or 32.  Line buffer 2 stores 2xNxM bits;
NxM is the horizontal width of the raw image.  Line buffer 2 holds
the latest two lines of raw image.  L sets of 3x3 masks modify the
raw image data and generate new image data, which are written back to
image buffer 1.  L is defined by the different operating speed of
image buffer 1 and the mask circuit; L is typically (N/4), and the
mask circuit, a combinational circuit in the gate array, works with a
clock that is times faster than that of image buffer 1 and line
buffer 2, and has a big and slow memory.  The address counter of
image buffer 1 is a special zig-zag counter that increments and
decrements as follows:
0, ,1, ,2, ,3, , , , 2xNxM,,2xNxM+1,0,2xNxM+2,1,2xNxM+3,2
This special zig-zag counter increments by 2xNxM+2 and decrements by
2xNxM+1, thus tracing the different read-out addresses and write-back
addresses of image buffer 1.
Samples of 3x3 masks are as follows:
move-up     move-down   move-right  move-left
 0...