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Use of Dirty, Buffered, and Invalidate Bits for Cache Operations

IP.com Disclosure Number: IPCOM000108494D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 48K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

The IBM RISC System/6000* contains an I/O Channel Controller (IOCC) which generates the MICRO CHANNEL* bus. The IOCC contains a pool of sixteen, 64-byte DMA buffers to provide a robust channel to/from system memory and the MICRO CHANNEL. For bus Master operations, software dynamically allocates certain buffers to each active bus Master device. Since bus Master operations are not necessarily sequential and multiple buffers can be allocated to each device and multiple devices can be allocated to each buffer, the management of these buffers becomes an interesting problem.

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Use of Dirty, Buffered, and Invalidate Bits for Cache Operations

       The IBM RISC System/6000* contains an I/O Channel
Controller (IOCC) which generates the MICRO CHANNEL* bus. The IOCC
contains a pool of sixteen, 64-byte DMA buffers to provide a robust
channel to/from system memory and the MICRO CHANNEL.  For bus Master
operations, software dynamically allocates certain buffers to each
active bus Master device. Since bus Master operations are not
necessarily sequential and multiple buffers can be allocated to each
device and multiple devices can be allocated to each buffer, the
management of these buffers becomes an interesting problem.

      To increase performance, provide data security and minimize
control complexity, the IOCC treats these buffers as pseudo-caches by
the use of one Least Recently Used Address (LRUA) per buffer, and
three control bits per buffer, Dirty(D) bit, Buffered(B) bit, and
Invalidate(I) bit.  The following table shows the definitions of
these three bits:
      D B I                  Definition
      0 1 0   Buffer has been prefetched from system memory.
      1 1 0   Buffer has been prefetched from system memory and then
written with DMA data.
      1 0 0   Buffer contains sequential dirty DMA data from the
beginning with the rest of the data being zeros.
      0 0 0   Buffer contains all zeros.
      X X 1   Buffer contains some old "stale" data.

      To improve sequen...