Browse Prior Art Database

X.21 Network Status Determination at Initialization Time

IP.com Disclosure Number: IPCOM000108507D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Alcantar, JM: AUTHOR [+3]

Abstract

In developing a communications adapter that supports the CCITT X.21 interface for the IBM RISC System/6000*, high performance dictated the use of hardware logic to handle all front-end functions. One of these functions is to determine the state of the X.21 network when the adapter is being initialized. Since this state is time dependent, special logic must be implemented to insure the correct interpretation.

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X.21 Network Status Determination at Initialization Time

       In developing a communications adapter that supports the
CCITT X.21 interface for the IBM RISC System/6000*, high performance
dictated the use of hardware logic to handle all front-end functions.
One of these functions is to determine the state of the X.21 network
when the adapter is being initialized.  Since this state is time
dependent, special logic must be implemented to insure the correct
interpretation.

      This invention provides the means to determine the X.21 network
status when the Data Terminal Equipment (DTE) is initially attached
to the X.21 network.  Referring to Fig. 1, the design allows the use
of existing logic and software with minor additional logic.  The X.21
network State Change Counter-Programmable Array Logic (SCC-PAL) is
designed to detect and inform the host whenever a state change occurs
in either Received Data (RxD) or Indicate (I(r)).  The problem at
initialization time is that these two signals may have been changed
by the X.21 network before the SCC-PAL was enabled and will not
change until the DTE responds.  The DTE will not know that it needs
to respond because the SCC-PAL was disabled when the state change
occurred; hence, the X.21 network and the DTE are effectively locked.

      The design uses a latch external to the SCC-PAL to create a
delayed Indicate (I(d)).  As shown in Figs. 2 and 3, I(d) is delayed
by one clock time.  I(r) and I(d) are inputs to...