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BiCMOS Circuit with Optimum FET Operating Voltages

IP.com Disclosure Number: IPCOM000108527D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+5]

Abstract

As FET oxide thickness (Tox) and effective length (Leff) decrease to improve performance and density of CMOS/BiCMOS, the breakdown voltages of these smaller FETs also decrease. This requires the FET operating voltages to also decrease. When the power supply voltage of BICMOS is decreased below 3 V, the circuit delay increases rapidly. The new BICMOS circuit described in this article improves the performance by reducing selectively the maximum drain to source applied voltages and increasing other voltages such as the gate-to-source across the FET section. This is accomplished at a higher power supply voltage.

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BiCMOS Circuit with Optimum FET Operating Voltages

       As FET oxide thickness (Tox) and effective length (Leff)
decrease to improve performance and density of CMOS/BiCMOS, the
breakdown voltages of these smaller FETs also decrease.  This
requires the FET operating voltages to also decrease.  When the power
supply voltage of BICMOS is decreased below 3 V, the circuit delay
increases rapidly.  The new BICMOS circuit described in this article
improves the performance by reducing selectively the maximum drain to
source applied voltages and increasing other voltages such as the
gate-to-source across the FET section.  This is accomplished at a
higher power supply voltage.

      Fig. 1 is a schematic of a state-of-the-art NAND BICMOS
circuit.  The operating voltages in Table Ia) are listed for the
switching N- FETs shown in the schematic of Fig. 1. From Table Ia),
it can be seen that Vds reaches a value of  Vdd  for the N-FETs in
the CMOS section.  Therefore, the power supply cannot be any higher
than the maximum allowed value of Vds.  Note (1) refers to the N-FET
which when turning on supplies base current to the bottom bipolar
device.  This bipolar device pulls down the output to the "Low"
state.  It is therefore desirable to maximize the Vgs of the N-FET in
the Pull-Down section to increase the base current to the bipolar
pull-down device.  When Vdd decreases to 2.5 V, Vgs becomes equal to
2.5 - 1.4 = 1.1 V which is not high enough to develop sufficient...