Browse Prior Art Database

Parallel Access to Multiple Adapter Components

IP.com Disclosure Number: IPCOM000108541D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 6 page(s) / 235K

Publishing Venue

IBM

Related People

Gyllenhammer, CR: AUTHOR [+2]

Abstract

Most adapter designs make use of "off the shelf" components to save on design time and money.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 30% of the total text.

Parallel Access to Multiple Adapter Components

       Most adapter designs make use of "off the shelf"
components to save on design time and money.

      One of the drawbacks to using these types of components is
that, since they are designed to work in as many different
environments as possible, many are designed with smaller interfaces
to make them more versatile.  They are usually designed with a fully
interlocked (asynchronous) interface and it is not unusual for these
devices to require a "recovery time" between each transfer.

      Since most designs utilize "off the shelf" components, most
microprocessors have been designed to be a "hybrid" processor so that
it cannot only be used for high-speed data transfer (i.e., the
microprocessor possesses a large data bus), but also can support many
other "off the shelf" components that were not designed for
high-speed transfers (i.e., parts containing small data buses).
Usually the instructions dealing with I/O (instead of the high-speed
memory) are relatively slow.

      Generally, some support logic is used to tie the microprocessor
in with the rest of the adapter.  This logic is often used to assist
with generating the signals needed for the microprocessor to
communicate.

      The most widely used solution for a "fast" microprocessor
interfacing to a "slow" component is to use only part of the
microprocessor's data bus when talking to the "slow" component.  This
solution works but it underutilizes the microprocessor and this is
never desirable.

      Another solution is to design all components needed to support
large data buses.  This solution allows the microprocessor to operate
at its maximum efficiency, but it costs more for development and
almost always more for the component.

      A far better solution is to select "off the shelf" components
that have similar interfaces (although they may not perform similar
function) and place them on different sections of the microprocessor
data bus (Fig. 1).  This would allow the microprocessor to access
multiple components during a single data transfer cycle.

      This solution allows the use of cheap "off the shelf"
components while minimizing their negative effects on the
microprocessor's performance.

      There are other possible savings depending on the specific
adapter implementation.  Certain designs could use less address
space, less support hardware, etc.  These savings, however, are
dependent on how the microprocessor sub-system is designed.

      Depending on the function to be performed and the
microprocessor selected, the sub-system logic can be designed to
allow the microprocessor maximum versatility. This is very system
dependent and must be designed to the particular systems needs.  In
this article, an example of a microprocessor and sub-system design
are shown.

      The microprocessor used in the example has the following
characteristics.
       .   The Micr...