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Method of Generating a Defined Clock Spacing

IP.com Disclosure Number: IPCOM000108550D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Haess, J: AUTHOR [+4]

Abstract

The described method allows a spacing of 1.5 to 2.5 ns between two clock signals (Fig. 1), with adverse temperature and supply voltage effects being compensated for.

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Method of Generating a Defined Clock Spacing

       The described method allows a spacing of 1.5 to 2.5 ns
between two clock signals (Fig. 1), with adverse temperature and
supply voltage effects being compensated for.

      The logic chips are provided with a digital speed control
(DISCO) for the output drivers.  DISCO supplies output signals from
which the actual delays on the chips are derivable.  These signals
are used to connect logic gates to the clock signal chain depending
upon the actual delays on the chips (Fig. 2).

      Of the ten DISCO 1 speed lines, at least one is switched on.
The slower the chip, the higher the number of active speed lines.
From the speed line information, decoder 2 generates a 1-out-of-5
code (Fig. 3).  This code is stored in latches 3.  As a result, the
entire circuit element may be LSSD (level sensitive scan design)
tested (see shift chain).  In addition, the decoder output may be
sensed for the chip speed.

      As a function of the code, the number of gates between A-clock
generation and output drivers is varied.  For chips with short delays
(small number of active speed lines), the signal has to pass more
stages than with chips having long delays (large number of active
speed lines).  The delays are fine-adjusted by the logic stages
selected (AND or NAND) and by manually controlling the line lengths
and capacities during the physical design process.

      The delays are also adjustable by means of the service
processor, so that the clock spacing is adjustable, too, without
using DISCO.

      The operational cycle is as follow...