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Clock Skew Aligner

IP.com Disclosure Number: IPCOM000108562D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Kohler, H: AUTHOR [+3]

Abstract

This article describes a system for the automatic alignment of clock pulses which are generated on a particular chip for distribution to a number of chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Clock Skew Aligner

       This article describes a system for the automatic
alignment of clock pulses which are generated on a particular chip
for distribution to a number of chips.

      As shown in Fig. 1, each chip #1...#n is supplied with a return
clock Cr(x) for flight-time measurement.  In addition, a clock Cref
is used.

      The Cref clock is compared with all Cr(x) clocks and moved back
by a programmable delay line PDEL until it encounters the latest
Cr(x) clock received.  As a result, all other Cr(x) clocks arrive
before Cref.  The time delta 2dT between Cref and the returning Cr(x)
clocks represents the relative clock flight-time delta from the clock
chip to the other chips and back.  Tf represents the forward clock
flight time resulting from the total delay of module, card, board,
card and module; Tr is the summarized return clock flight time.

      To correct the dT's (clock skews), half the measured time delta
is added to the appropriate C(x).  For symmetrical alignment, the
other half is added to the returning Cr(x).  As a result, the clock
edges in all user chips are synchronized.

      If there is a temperature, voltage or impact-dependent drift of
the propagation time in the delay lines, fewer stages are
automatically used to measure 2dT against Cref.

      The dT measurement is performed continuously until 'Reset' or
'Hold' is activated by the run control logic.
Stage 1

      After power on, all Cr(x) clocks are di...