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High-Speed Intel 80486 External Cache Bus Structure Disclosure Number: IPCOM000108568D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 162K

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Begun, RM: AUTHOR [+2]


This article describes building an external cache memory for the 80486 at 40 MHz and above with static random-access memory (SRAM) technology.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Speed Intel 80486 External Cache Bus Structure

       This article describes building an external cache memory
for the 80486 at 40 MHz and above with static random-access memory
(SRAM) technology.

      While the 80486 has an internal cache, it is desirable to have
a large external cache.  The external cache improves the total cache
hit ratio from the 80 percent range to the upper 90 percent range.
The internal 80486 cache is organized with a cache line size of 16
bytes or four dwords. If the 80486 generates a read request to a
cacheable memory location, it will initiate a complete cache line
fill of four dwords.  The external cache is architected to provide
the complete cache line if a hit occurs.  It is known through
research that a two-way set associative cache can provide a higher
hit ratio than a direct map cache design with minimal increase in
complexity.  Therefore, the external cache disclosed herein is
architected as a four dword line, two-way set associative design, as
illustrated in Fig. 1.  The overall size of the cache is determined
by how many cache lines are in each set.

      The 80486 will always request the dword that is required to
continue execution first.  The first dword can be any one of the
dwords in the cache line.  The order of subsequent dword reads to
finish the cache line fill is always predictable.  This
predictability allows the external cache to access all four dwords of
the cache line in parallel.  The data is provided to the 80486 by
simply using SRAM modules with tri-state outputs and gating each
dword onto the bus in the correct order.  By using the tri-state
outputs, all of the dwords are connected on a cache data bus, as
depicted in Fig. 2.  This simple bus structure works well with SRAM
technology and 80486 speeds of less than 40 MHz while still
maintaining 1 clock zero waitstate accesses.

      To maintain single clock data accesses at 40 MHz and above with
the SRAM technology, a creative bus structure is required.  The
creative bus structure takes advantage of the predictability of the
80486 cache line fill order.  This creative bus structure is referred
to as the intermixed two-way bus.  The inter-mixed two-way bus
introduces two separate buses for the cache data SRAM, as depicted in
Fig. 3.  As in the simple bus structure, the inter-mixed bus
structure address accesses all the dwords in the cache in parallel
for the first access.  In the concept of this disclosure each of the
two-way set dwords are inter-mixed on the two buses to allow early
overlapped accesses of subsequent dwords reads once the set hit
decision is made.

      Fig. 4 shows the waveforms for the simple 8...