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Dual-Bus Arbitration for Personal Computer Systems

IP.com Disclosure Number: IPCOM000108584D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 178K

Publishing Venue

IBM

Related People

Alderequia, A: AUTHOR [+5]

Abstract

Described is an arbitration mechanism which provides processor and cycle concurrency, in dual bus personal computer (PC) systems equipped with the Micro Channel* (MC) by utilizing dual-port memory controller sequencers. Protocol principles and sequencer states are also described.

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This is the abbreviated version, containing approximately 46% of the total text.

Dual-Bus Arbitration for Personal Computer Systems

       Described is an arbitration mechanism which provides
processor and cycle concurrency, in dual bus personal computer (PC)
systems equipped with the Micro Channel* (MC) by utilizing dual-port
memory controller sequencers. Protocol principles and sequencer
states are also described.

      In single-bus systems, whenever a MC bus master requests
control of the bus, the central processing unit (CPU) must relinquish
control of the bus.  The CPU must either run out of its internal
cache or remain idle until the requesting bus master relinquishes
control of the bus. As a result, there is no cycle concurrency
between the CPU and the bus masters.  In dual-bus PC systems, cycle
concurrency is allowed between the CPU and the bus masters since the
CPU and the system/MC data buses are isolated by a memory controller.
The block diagram shown in Fig. 1 illustrates this configuration.

      In the dual-bus architecture, the CPU can always execute cycles
to resources on the bus, such as to read-only memory (ROM), cache, or
a coprocessor.  The memory controller is responsible for arbitrating
ownership of the system/MC bus and planar memory; however, cycle
concurrency may not occur.

      The concept described herein provides a means whereby cycle
concurrency can occur.  Figs. 2a and 2b show an example of the cycle
concurrency arbitration implementation. The 'X' indicates the cycle
being executed on the CPU, or the bus master.  The accompanying line
indicates the allowable cycle concurrency.  In Fig. 2a, the CPU is
accessing the local bus indicated by the 'X'.  In Fig. 2b, the bus
master can execute a cycle to the planar memory and channel
resources.

      The memory controller (not shown) has two independent
sequencers:  one for the CPU bus cycles and one for the system bus
cycles.  The sequencers must provide the concurrent cycle operation
so as to handle asynchronous requests for the MC resources, or the
planar memory resources from the CPU or bus masters.  In addition,
provisions are added for handling locked bus cycles, cache hit/abort
cycles and the active time violation timer.

      A set of rules is defined to control the interaction of the
sequencers and to determine who controls access to the planar memory
and the system/MC bus.  The ownership of the system bus and the MC
bus is treated as one physical unit. The memory controller has two
independent sequencers, as shown in Figs. 3a and 3b.  Fig. 3a shows
the CPU bus sequencer and Fig. 3b shows the system bus sequencer.
The CPU bus sequencer (Fig. 3a) interfaces to the CPU bus and drives
the control signals required to execute cycles to the planar memory
and the channel resources.  The system bus sequencer (Fig. 3b)
interfaces to the system and the MC buses and drives the output
signals required to interface to the planar memory.

      A sequencer is a set of states with defined output and
conditio...