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Browse Prior Art Database

Cache Coherency Cache Directory Table

IP.com Disclosure Number: IPCOM000108596D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+2]

Abstract

This article describes an architecture to maintain cache coherency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Cache Coherency Cache Directory Table

       This article describes an architecture to maintain cache
coherency.

      One of the problems encountered when multiple bus masters are
placed in a system, as shown in Fig. 1, is maintaining cache
coherency.  This is especially complicated if one or more of the bus
masters contain local shared memory (shared memory that can be
accessed by any of the bus masters, but the access by the local bus
master is not reflected on the system bus).  Bus master 2 does a
memory read of local shared memory (shared by bus master 1 and 2, but
local to bus master 1 only).  It stores this data in its cache.  Bus
master 1 does a memory write to its local memory at the same address
where bus master 2 read the data.  Since this access is not posted on
the system bus, bus master 2 is unaware of the data change.  Bus
master 2 does a read of the same address as before.  Realizing that
this address is in cache, it reads the data from cache without
realizing that this data is stale.

      One way to fix this is through software.  However, the
architecture disclosed herein is a hardware solution.

      Referring to Fig. 2, a cache directory table (TAG RAM) is
provided in the arrangement of Fig. 1 that latches addresses of local
memory that have been read by an external bus master.  This TAG RAM
keeps a tag of all the addresses that have been accessed by the bus
masters.  A CPU write to local shared memory previously accessed by...