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Interrupt Status Port Extension to the Subsystem Control Block Architecture

IP.com Disclosure Number: IPCOM000108603D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 149K

Publishing Venue

IBM

Related People

Bonevento, FM: AUTHOR [+3]

Abstract

This article describes a technique for use in a computer system when a subsystem supports multiple commands per device and/or supports a method of command queuing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Interrupt Status Port Extension to the Subsystem Control Block Architecture

       This article describes a technique for use in a computer
system when a subsystem supports multiple commands per device and/or
supports a method of command queuing.

      This technique provides a direct address of a subsystem control
block (SCB) which requires interrupt processing rather than requiring
the program to determine the SCB address from device data provided at
the point of interrupt. It provides data at the point of interrupt
which allows a program to determine the Non-SCB command which has
caused an interrupt.

      Further, it provides the address of the SCB when a hardware
failure occurs during processing SCB, and no termination status block
(TSB) status can be stored in the host processor memory.
THE ISPE EXTENSION INTRODUCTION

      The method of this disclosure extends the SCB architecture by
adding a 32-bit port, the Interrupt Status Port Extension (ISPE),
which is used with the Interrupt Status Port (ISP) to give the
interrupt handler detailed data on interrupts.  The ISPE is set and
cleared wherever the ISP is set and cleared, and only contains a
valid value when the IV bit in the Command Busy Status Port is one.

      The ISPE contains the following information:
      1.   The Non-SCB command (immediate command) which caused the
interrupt to be raised.  If the subsystem is capable of accepting
multiple commands per device, this value would indicate to the
initiator the non-SCB command which caused the interrupt to be
raised.
      2.   When the hardware controlled Reset Subsystem is executed,
the ISPE value allows an interrupt handler to distinguish the
hardware controlled Reset Subsystem from a software controlled Reset
Device to device zero, which resets the subsystem under software
control and does not necessarily execute Power-on Self-test (POST) or
reloading of the subsystem internal code.  The hardware controlled
Reset Subsystem causes the value "80000000"x to be stored in the
ISPE, when the command completes with no error, or when the subsystem
fails with a hardware failure while executing a hardware-controlled
Reset Subsystem. A software-controlled Reset Subsystem will never
have bit 31 of the ISPE equal to one.
      3.   The address of the SCB which requested the interrupt is
queued in the device's interrupt queue when a SCB command completes
and requests an interrupt.  The SCB address is also placed on the
interrupt queue for the device when the SCB completes indicating that
the SCB could not be fetched, or that the TSB could not be stored.
ISPE FORMAT

      The ISPE is a 32-bit-wide port which is defined in I/O address
space.  It is allocated at the next contiguous I/O address after the
Subsystem Control port.  The port is not optional, and is used in
conjunction with the interrupt status port to provide interrupt
status data to the host program.  The port is read-only t...