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Programmable Interconnection Switch Structure for Large Scale Machine Prototyping

IP.com Disclosure Number: IPCOM000108611D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 148K

Publishing Venue

IBM

Related People

Jackson, RD: AUTHOR [+4]

Abstract

This article describes and illustrates a methodology and hardware that can provide a programmable prototype environment which is scalable to large digital systems design. A unique switch chip is presented which is specifically designed to allow reprogrammable signal interconnections on a large scale. The switch has features that allow it to emulate a prototype design's machine cycle with multiple subcycles and switch settings, so that its connection resources can be time shared.

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This is the abbreviated version, containing approximately 51% of the total text.

Programmable Interconnection Switch Structure for Large Scale Machine Prototyping

       This article describes and illustrates a methodology and
hardware that can provide a programmable prototype environment which
is scalable to large digital systems design.  A unique switch chip is
presented which is specifically designed to allow reprogrammable
signal interconnections on a large scale. The switch has features
that allow it to emulate a prototype design's machine cycle with
multiple subcycles and switch settings, so that its connection
resources can be time shared.

      Furthermore, the article describes a system configuration in
which the switch chip can be used, and a methodology which would
facilitate a full system soft programmable prototyping environment.

      This article proposes the use of groups of Field Programmable
Gate Arrays (FPGAs) to emulate islands of related logic, such as a
gate array or a logic board. A group of FPGAs is thought of as being
on a small board or multi-chip carrier in a fixed connected pattern
but still soft programmable from external control interface. The
group of FPGAs on a carrier is called an FPGA element.

      The FPGA elements are further connected to each other by one or
more special soft programmable prototyping boards or backplanes to
form a system. Cables and/or additional soft programmable backplanes
may be used to connect from one board to another.

      Any number of the soft programmable boards can be assembled
into a soft programmable system which would have a host control
computer and a prototype interface adapter (see Fig. 1).  The
interface adapter would provide a programming interface to the boards
and FPGA elements. The interface also provides control signals and
clocking to the prototyping hardware.

      Finally, vendor tools can be used to capture a system design
for prototyping.  Standard methodology typically results in a
partitioning of the system into islands of logical function connected
by a net list.  The islands of logical function are further processed
into programming vector files that serve to personalize FPGA
elements. The net list is processed by special signal routing
programs that produce programming instructions for the switch chips
on the soft programmable printed circuit boards.

      The soft prototyping boards may also be referred to as
programmable printed circuit boards. The boards consist mainly of a
dense matrix arrangement of special switch chips also proposed in
this article and described later. The switch chips on the prototyping
boards have a certain portion of their pins connected to the pins of
the FPGA element locations of which  there are several evenly
distributed over the board surface. The remainder of the switch pins
are connected to neighboring switch chips in a fixed pattern. The
fixed connection pattern between switch chips is further divided into
connections that are to nearest neighbor switch chips an...