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Socketless Coprocessor for Personal Computers

IP.com Disclosure Number: IPCOM000108619D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 137K

Publishing Venue

IBM

Related People

Mosley, JM: AUTHOR [+2]

Abstract

Described is an arrangement for mounting optional coprocessor modules relative to associated processor modules, on multi-chip cards or boards used in computer systems. Two variations of a basic mounting arrangement are shown.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Socketless Coprocessor for Personal Computers

       Described is an arrangement for mounting optional
coprocessor modules relative to associated processor modules, on
multi-chip cards or boards used in computer systems.  Two variations
of a basic mounting arrangement are shown.

      In prior arrangements, a printed circuit card (or board)
contains multiple chip modules, which are mounted on one surface of
the card and interconnected by means of printed circuit wiring within
the card.  One module contains a processor (or microprocessor), and,
typically, a socket is provided on the card surface for attachment of
an optional coprocessor module.  The socket is connected by printed
circuit wiring to pin terminals of the processor module. With module
circuits operating at ultra-high clock speeds (e.g., above 40 MHz),
this type of arrangement may introduce unacceptable delays and
distortions of critical signals required to pass directly between the
processor and coprocessor (e.g., clock signals).  Such delays and
distortions are associated with the socket structure per se and
impedances presented by the card or board media and connecting
printed circuits.

      In the present arrangement, the coprocessor and processor
modules mount in-line, on opposite sides of a card or board, and
connect without printed circuit wiring.  This eliminates the socket
structure of prior arrangements, and shortens the lengths of all
connections between the processor and coprocessor, thereby further
reducing signal delays and/or distortions.  Furthermore, the
essentially equal lengths of all connections between the processor
and coprocessor eliminates skewing of critical clock signals
associated with prior arrangements.

      Fig. 1 shows the basic arrangement.  Multi-chip ceramic module
chip module package 10, containing a processor or microprocessor (not
shown) module and other devices, is equipped with an array of
conductive pins 11 hereafter termed the pin grid array (or PGA).
Package 10 is supported on a printed circuit card 12 (e.g., epoxy
glass), with pins 11 extending through the card and beyond the bottom
surface of the card. Coprocessor options are provided on ceramic chip
packages 13, each equipped with an array of bifurcated conductive
pins 14 designed to align with the PGA array on package 10.  Thus, a
coprocessor option...