Browse Prior Art Database

Crossbar Switch for a Superscaler Processor

IP.com Disclosure Number: IPCOM000108632D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+2]

Abstract

Disclosed is a structure that helps organize the large number of wires that are common in superscaler processors. A recognized problem with superscaler processors is a large switch structure between instruction dispatch and instruction execute. There is also a switch structure between execute and instruction write back. The large numbers of wires that might cross at these points have been a concern in a very wide superscaler design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 92% of the total text.

Crossbar Switch for a Superscaler Processor

       Disclosed is a structure that helps organize the large
number of wires that are common in superscaler processors. A
recognized problem with superscaler processors is a large switch
structure between instruction dispatch and instruction execute.
There is also a switch structure between execute and instruction
write back.  The large numbers of wires that might cross at these
points have been a concern in a very wide superscaler design.

      This article describes how the register file and rename buffers
can be incorporated into a crossbar switch that organizes the large
number of wire crossings.  The crossbar switch organizes the wires
into a rotary pattern that is flexible for different numbers of
execute units.

      The figure represents the major crossbar elements of the
processor.  The following letters represent the different functions
of the crossbar switch:
      A - Rename buffers and input mux
      B - Rename buffers to execute mux
      C - GPR register and input mux
      D - GPR registers to execute mux
      E - Execute unit output muxes

      As instructions are dispatched,  data must move from the rename
buffers and GPR registers to the execute units. This is represented
as a flow from A to B to execute units and C to D to
execute units. As data is produced in the execute units, the data
must flow to the rename buffers. This is represented by dataflow from
exe...