Browse Prior Art Database

Timing Verification Model for Personal Computer Systems

IP.com Disclosure Number: IPCOM000108635D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Van Asten, G: AUTHOR

Abstract

Described is a software tool that provides an automatic timing verification model for personal computer (PC) systems equipped with the Micro Channel* (MC). The model is used to verify a total of ninety-four timing parameters. In addition, a guardband feature is included to aid product designers with timing parameter analysis.

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This is the abbreviated version, containing approximately 52% of the total text.

Timing Verification Model for Personal Computer Systems

       Described is a software tool that provides an automatic
timing verification model for personal computer (PC) systems equipped
with the Micro Channel* (MC).  The model is used to verify a total of
ninety-four timing parameters.  In addition, a guardband feature is
included to aid product designers with timing parameter analysis.

      The timing verification model for PC systems is designed to
simplify the verification of a design's conformance to the MC
architecture.  By using the model, designers save time by not having
to analyze the results of every test case.  Product quality is
improved through a comprehensive timing verification of the design.
The guardband feature is provided to allow designers the ability to
check on how close design timings are to the allowed timing
specifications.

      The concept described herein is designed to provide a timing
verification model and to provide an automated means of verifying the
bus timings for any MC device.  The model acts as a passive device
that connects to the MC bus so as to verify ninety-four timing
parameters, as defined in the PC technical reference manual for the
MC.  The model also includes a guardband feature to enable the
designers to determine how close a design is to the allowed timing
limits.  Messages are displayed when timing violations occur and may
be controlled by an input to the model.  An output is provided from
the model to indicate an error and may be monitored by the test case
specified.

      The software for the model is written and controlled by the
test cases through model facilities.  These facilities control the
guardband and message display functions and provide error status
registers for the model.  The local timing verification model
facilities are listed as follows:
     MCK1_MASK(1)   - Timing verification disabled if set to 0.
     MCK1_MIN_MIN   - Time to subtract from min. timing parameters.
     MCK1_MIN_MAX   - Time to add to minimum timing parameters.
     MCK1_MAX_MIN   - Time to subtract from max. timing parameters.
     MCK1_MAX_MAX   - T...