Browse Prior Art Database

Programmable PIO Preemption Due to Bytes Transferred

IP.com Disclosure Number: IPCOM000108642D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

Programmable Input/Output (PIO) operations are issued by processors to send/receive information to/from I/O devices. These I/O devices typically reside on a common I/O bus to minimize system interfaces. Direct Memory Access (DMA) operations are performed by certain I/O devices to improve system performance. This structure creates a bottleneck on the I/O bus when the processors and DMA devices are contending for bus usage. Typically, to improve system performance, the DMA devices have a higher priority than the processors. This, however, may cause long PIO string operations to go through multiple arbitration sequences to complete the entire transfer, thus, degrading PIO performance.

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Programmable PIO Preemption Due to Bytes Transferred

       Programmable Input/Output (PIO) operations are issued by
processors to send/receive information to/from I/O devices. These I/O
devices typically reside on a common I/O bus to minimize system
interfaces.  Direct Memory Access (DMA) operations are performed by
certain I/O devices to improve system performance.  This structure
creates a bottleneck on the I/O bus when the processors and DMA
devices are contending for bus usage.  Typically, to improve system
performance, the DMA devices have a higher priority than the
processors.  This, however, may cause long PIO string operations to
go through multiple arbitration sequences to complete the entire
transfer, thus, degrading PIO performance.

      The overall system performance is dependent on the balance
between these PIO and DMA operations on the I/O bus. In turn, the PIO
and DMA usage of the I/O bus is dependent on the task(s) being
performed by the processor.  To optimize these cases, a Configuration
Register may be added to the I/O Channel Controller (IOCC) to allow a
programmable number of bytes to be transferred before the PIO
operation relinquishes the I/O bus.  This would then allow long PIO
string operations to go through fewer arbitration sequences, as well
as potentially performing the transfers in an enhanced block transfer
format (i.e., Micro Channel* Streaming Data procedure).  Also,
providing atomic PIO capability on the I/O bus increases...