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Optimization of Mobility without Threshold Voltage Degradation

IP.com Disclosure Number: IPCOM000108654D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Aitken, J: AUTHOR [+6]

Abstract

A process is described which optimizes the channel profile of small dimension FET devices so that the mobility of carriers at the surface of the device is maximized while the threshold voltage is maintained at a level necessary to prevent punch through. Such requirements demand a very sharp retrograde profile such as the one described in (1). The threshold voltage of the device is maintained by a distribution of dopant which is separated from the channel region to prevent surface scattering and high field effects that degrade the carrier mobility in the channel. The channel region controlling transport is less than 10 nm thick. This consideration is especially important in the case of low temperature operation of devices since surface scattering is the predominant detractor of mobility.

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Optimization of Mobility without Threshold Voltage Degradation

       A process is described which optimizes the channel
profile of small dimension FET devices so that the mobility of
carriers at the surface of the device is maximized while the
threshold voltage is maintained at a level necessary to prevent punch
through.  Such requirements demand a very sharp retrograde profile
such as the one described in (1). The threshold voltage of the device
is maintained by a distribution of dopant which is separated from the
channel region to prevent surface scattering and high field effects
that degrade the carrier mobility in the channel.  The channel region
controlling transport is less than 10 nm thick.  This consideration
is especially important in the case of low temperature operation of
devices since surface scattering is the predominant detractor of
mobility. Other implementations have been proposed to achieve this
profile (1,2).  But each suffers from disadvantages which are taken
care of by the proposed process.  The use of LTE to deposit the
entire profile of the device including both the channel region and
the heavily doped threshold adjust region in the region defined by
the isolation is proposed in (1).  Unwanted material over the
isolation regions must then be removed by an etch selective to the
polycrystalline orientations of this material.  Etch pits which
extend into the single crystal at the edges of the single crystal
regions are a potential hazard.  The growth of undoped epitaxial
material on top of a heavily doped well region using conventional
epitaxial g...