Browse Prior Art Database

Packet Memory Controller Chip for Generic High Bandwidth Adapters

IP.com Disclosure Number: IPCOM000108655D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Chang, P: AUTHOR [+4]

Abstract

The Packet Memory Controller (PMC) of the Generic High Bandwidth Adapter (GHBA) chipset is described in this article.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Packet Memory Controller Chip for Generic High Bandwidth Adapters

       The Packet Memory Controller (PMC) of the Generic High
Bandwidth Adapter (GHBA) chipset is described in this article.

      The PMC controls the access to the packet memory (PM) by the
various entities connected to the Generic Adapter Bus (GAB).  The PMC
acts as a slave to the entities connected to the  GAB,  and  as a GAB
master in proxy for the 386 Support Chip (SC).  All necessary signals
for DRAM access and refresh are generated by the PMC.  This chip can
be used in all GHBA adapters using DRAMs for the packet memory and a
GAB cycle time of 80 ns.

      The chip was implemented in CMOS 2.1 20K gate array technology,
with a die size of 9.4 x 9.4 mm, and 183 I/O's.

      The PMC is a slave to the various devices on the GAB. In
addition, it acts as a GAB master in proxy for the 386 support chip
to allow the 386 to access the GAB.

      The PMC generates the signals necessary for DRAM access.  These
include RAS, CAS, write enable, and output enable.

      It is the responsibility of the PMC to generate and check ECC
on the data it stores in the PM.  It has the responsibility of
generating data and address parity when it is GAB master and checking
them when it is a slave.

      Since the memory to be used in the PM is DRAM, the PMC also
has the responsibility for periodic refresh, and the arbitration
between this refresh and normal accesses.

      The PMC...