Browse Prior Art Database

Universal Self Test Structure

IP.com Disclosure Number: IPCOM000108659D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Doney, R: AUTHOR [+2]

Abstract

This disclosure modifies the self-test boundary structure disclosed in U.S. Patent 5,042,034 by adding logic 'MACRO C', which extends disclosure in U.S. Patent 5,042,034 to higher levels of self-test structures like cards, boxes, and systems. The figure shows logic 'MACRO C' as it is applied to the chip, card, and box.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Universal Self Test Structure

       This disclosure modifies the self-test boundary structure
disclosed in U.S. Patent 5,042,034 by adding logic 'MACRO C', which
extends disclosure in U.S. Patent 5,042,034 to higher levels of
self-test structures like cards, boxes, and systems.  The figure
shows logic 'MACRO C' as it is applied to the chip, card, and box.

      With reference to the figure, logic 'MACRO C' has three inputs
which enable the appropriate level of self-test.
1.   SYSTEM MODE - Configures the circuit into a self-test mode or a
functional mode.
2.   BOUNDARY - Once in self-test mode, this signal configures the
circuit into either accepting data from the primary inputs or from
the internally generated self-test patterns.  These internally
generated patterns are fed back from the registers through a
tri-state pass gate back onto the outputs of the primary inputs
receivers. The receiver in this case is tri-stated.  A boundary-pin
of a lower-level self-test could become a non-boundary-in of a
higher-level self-test.
3.   LEVEL (0..1) - This two-strand net configures the circuit into
either a chip, card, box, or system level self-test.  For example,
chip self-test has a level 00 and card self-test has a level 01, etc.

      Based on these signals, logic 'MACRO C' can enable the chip,
card, box, and system to be at different levels of self-test.  The
signature registers that are not showing in the figure are also
configured according to the l...