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Hardware Assist for Interlocked LOAD and LOAD AND TEST Instructions

IP.com Disclosure Number: IPCOM000108667D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 6 page(s) / 238K

Publishing Venue

IBM

Related People

Blaner, B: AUTHOR [+2]

Abstract

Disclosed is a hardware assist that allows interlocked LOAD and LOAD AND TEST instructions to be executed in parallel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 30% of the total text.

Hardware Assist for Interlocked LOAD and LOAD AND TEST Instructions

       Disclosed is a hardware assist that allows interlocked
LOAD and LOAD AND TEST instructions to be executed in parallel.

      An instruction-level parallel or superscalar computer seeks to
issue and execute multiple instructions per machine cycle.
Frequently, however, this is not possible because of the existence of
dependencies between sequential instructions. If a second instruction
depends on the execution results of a first instruction, the second
must await the completion of the first before it can execute.

      One such sequence that occurs frequently in ESA/390* programs
is
           L      R, LOC_A
           LTR    R,R
The instruction L R, LOC_A (LOAD) loads data from storage location
LOC_A to general register R.  The instruction LTR R,R (LOAD AND TEST)
reads the contents of R, sets the condition code register (CC) based
on the contents of R and in accordance with the architectural
specification for LTR, then writes the contents unmodified back into
R.  The LTR is usually followed by a branch instruction that tests
the CC.

      Without some hardware assist, a superscalar machine cannot
execute the LOAD AND TEST in parallel with the LOAD since the former
must wait for the execution of the latter, where "execution" of the
LOAD means loading data from storage.  This disclosure describes such
an assist.  The assist will execute interlocked LOAD and LOAD AND
TEST instructions of the form shown in the example in parallel. An
infrequent alternate form of the example sequence,
           L      R, LOC_A
           LTR    S,R
where the LTR loads register S / R, is not handled by the mechanism,
though it could be with some minor changes.  It is assumed that some
mechanism insures that the instructions in this alternate sequence
are issued sequentially.

      The assist will be described in the context of an exemplary
pipelined, instruction-level parallel machine, part of which is
illustrated in Fig. 1.  The pipeline for this machine is defined as
follows:
Cycle     Description
IF        parallel instruction fetch by instruction unit
           (I-unit 101)
           instructions latched in instruction register-left (IRL
102) and instruction register-right (IRR 103)
ID        instruction decode from IRL 102 and IRR 103
           control storage (CS 104) access for instructions in IRL
102 and IRR 103
           latch microinstructions from CS 104 into AG-cycle
instruction register (AIR 105)
           prefetch GRs for AG cycle from AGR array 106
           latch GRs in address generation adder (AG 107) input
registers LA 108 and MA 109
AG        address generation by AG adder 107
           address transmitted on ABUS 110 and latched in AREG 111
           storage command transm...