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Browse Prior Art Database

AC Array Self Test

IP.com Disclosure Number: IPCOM000108670D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR

Abstract

This article describes a test technique that allows for a true AC test of on-chip embedded arrays. The embedded arrays are exercised and tested by applying pseudo-randomly generated test data through the functional paths of the data, control and address logic leading to and from the array. All on-chip embedded arrays are tested simultaneously.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

AC Array Self Test

       This article describes a test technique that allows for a
true AC test of on-chip embedded arrays.  The embedded arrays are
exercised and tested by applying pseudo-randomly generated test data
through the functional paths of the data, control and address logic
leading to and from the array. All on-chip embedded arrays are tested
simultaneously.

      This technique allows for an early AC test of the on-chip
embedded arrays.  The test can be applied on the chip stand-alone or
at the wafer level, thus allowing for an effective screening of chips
with array AC faults, before the chips are mounted on higher level
packages to be tested later for AC defects with RAS and/or functional
test patterns.

      This technique is also superior to the RAS/functional code for
detecting array AC faults because it solves the problem of isolating
the array AC fault to a chip and/or an on-chip embedded array.

      This technique also relies on pseudo-randomly generated test
vectors, so no storage buffer is required to store the test data.
And finally, the technique also allows for an effective and better
speed sorting of chips, since it exercises the majority of chip
paths, including the array functional paths.  This is because most
past self-test techniques elected to bypass the arrays completely
during self-test due to the difficulty of initializing embedded
arrays to a known, repeatable state.

      This test technique takes advantage of the existence of an
on-chip controller called Common On-chip Processor (COP), as
described in (*).  The COP is a self-test controller designed
originally for the IBM RISC System/6000* processor chip set to
perform self-test and other functions. In this technique, the COP
controls (see figure) the AC array self-test operation by:
      1.  Configuring the chip scan strings into a self-test
configuration called STUMPS, in which a PRPG (Pseudo Random Pattern
Generator) feeds random data into the scan inputs of the chip scan
channels and a MISR (Multiple Input Signature Register) receives the
chip response (signature) in the form of test data captured in the
chip scan channels and compressed into the MISR.
      2.  Taking control of the chip clocks.
      3.  Controlling the PRPG and MISR for pseudo-random test data
generation and test response compression (signature).

      The COP PRPG (see figure) generates the pseudo-random test
vectors, and the vectors are scanned into the chip scan channels.
The Array DATA_IN and DATA_OUT registers are an integral part of chip
scan channels and get loaded with pseudo-random test vectors.  The
same is true for the array ADDRESS and array R/W control registers.

      The COP MISR compresses the chip scan channel test data and
stores the signature.

      The COP ADDRESS STEPPER is used to initialize the embedded
arrays to a known, random, repeatable state before AC array self-test
can start.  The COP i...