Browse Prior Art Database

Microcode Cycle Time Reduction Technique via Available Hardware Bus (serial Port) and Bridge Code at Both Ends

IP.com Disclosure Number: IPCOM000108687D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 154K

Publishing Venue

IBM

Related People

Bracken, B: AUTHOR [+6]

Abstract

Described is a method that can be used to emulate hardware using emulation software and off-the-shelf hardware to test microcode before the actual future hardware is available. This method includes the following: 1. Software (emulation code) to emulate future hardware interface logic which includes emulating the hardware functions and the transmission of data across the interface. 2. Off-the-shelf parallel or serial hardware to provide interfaces that allows future hardware emulation. 3. Additional emulation code on an existing system to provide a complete bridge for complete testing capability.

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Microcode Cycle Time Reduction Technique via Available Hardware Bus (serial Port) and Bridge Code at Both Ends

       Described is a method that can be used to emulate
hardware using emulation software and off-the-shelf hardware to test
microcode before the actual future hardware is available. This method
includes the following:
1.   Software (emulation code) to emulate future hardware interface
logic which includes emulating the hardware functions and the
transmission of data across the interface.
2.   Off-the-shelf parallel or serial hardware to provide interfaces
that allows future hardware emulation.
3.   Additional emulation code on an existing system to provide a
complete bridge for complete testing capability.

      This approach can emulate custom-designed hardware on a card
whose main components are an available microprocessor with memory and
off-the-shelf hardware and emulation code that provide the future
hardware interfaces (Figure 1).  It assumes that the microprocessor
and the memory are available long before the future hardware
interface logic.  Parallel or serial interface hardware work very
well when emulating hardware whose major function is message and data
traffic. A prototype card can be produced with the microprocessor,
the memory and off-the-shelf parts to provide a parallel or serial
interface to emulate the future hardware interface logic (Figure 2).

      On a typical midrange system, as shown in Figure 3, the PU
(Processor Unit) communicates over an intersystem bus to an IOP (I/O
processing element).  The code being tested on the prototype hardware
is the IOP code.  This approach provides a way to test this code
using a tester (see Figure 3 environment 1) or using an
underdevelopment PU or an existing PU for system level testing (see
Figure 3 environments 2 and 3).
PROTOTYPE
      o    All three environments have the same prototype.
      o    The serial port connection is chosen since that hardware
is readily available for the prototype, the PC monitor, the 9371, the
9221 or any other system which may be chosen to drive the prototype
card.
      o    Prototype emulation code is used to emulate future
hardware interface logic which includes emulating the hardware
functions and the transmission of data across the interface.
      o    PU emulation code is used to provide a connection between
the processor and the serial port.
      o   ...