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Selective Line Lifting to Improve Chip Interconnect Reliability

IP.com Disclosure Number: IPCOM000108702D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Chen, WT: AUTHOR [+3]

Abstract

The major roadblock to accomplishing Direct Chip Attachment (DCA) of Silicon device chips to printed circuit carriers, using IBM C-4 technology, is the mismatch of the TCE (Thermal Coefficient of Expansion) between the device chips (TCE = 2.5 x 10 -6 in./in./degree C.) and the next level carrier, i.e., Epoxy Glass (TCE = 17 x 10 -6 in./in./degree C.). This mismatch in TCE causes the interconnections to break (crack) with thermal cycling, which occurs with the turn on/turn off of the computer. This problem is circumvented by backbonding the chip to the substrate and wirebonding between the chip and the substrate. The wires are flexible and accommodate the TCE mismatch. This backbone/wirebond technology is limited because the wire density is limited and the wires' location is not predetermined - the wires can flop around.

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This is the abbreviated version, containing approximately 67% of the total text.

Selective Line Lifting to Improve Chip Interconnect Reliability

       The major roadblock to accomplishing Direct Chip
Attachment (DCA) of Silicon device chips to printed circuit carriers,
using IBM C-4 technology, is the mismatch of the TCE (Thermal
Coefficient of Expansion) between the device chips (TCE = 2.5 x 10 -6
in./in./degree C.) and the next level carrier, i.e., Epoxy Glass (TCE
= 17 x 10 -6 in./in./degree C.).  This mismatch in TCE causes the
interconnections to break (crack) with thermal cycling, which occurs
with the turn on/turn off of the computer.  This problem is
circumvented by backbonding the chip to the substrate and wirebonding
between the chip and the substrate.  The wires are flexible and
accommodate the TCE mismatch.  This backbone/wirebond technology is
limited because the wire density is limited and the wires' location
is not predetermined - the wires can flop around.

      This article teaches a method of achieving flexible wires
between the chip and the substrate using IBM C-4 (flip chip)
technology.  It describes a method to achieve selective disbonding of
the circuit lines away from the printed circuit carrier for a
predetermined, desirable length.

      The adhesion of the copper printed circuit lines to the printed
circuit carrier is achieved by using a thin metal interface such as
chromium, nickel, zinc, etc., between the copper lines and the
substrate.  After fabricating the printed circuit carrier, the
complete carrier...