Browse Prior Art Database

Common Algorithm for Read/Write Data Alignment

IP.com Disclosure Number: IPCOM000108708D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR

Abstract

The Input/Output Channel Controller (IOCC) of the IBM RISC System/ 6000* contains a robust data flow to improve channel performance between the I/O devices and the system processor and memory. However, the original data flow caused a drastic increase in the chip size and wiring. This article describes one of the methods employed in the IOCC design to minimize logic without significantly degrading channel performance.

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Common Algorithm for Read/Write Data Alignment

       The Input/Output Channel Controller (IOCC) of the IBM
RISC System/ 6000* contains a robust data flow to improve channel
performance between the I/O devices and the system processor and
memory.  However, the original data flow caused a drastic increase in
the chip size and wiring.  This article describes one of the methods
employed in the IOCC design to minimize logic without significantly
degrading channel performance.

      The data flow for the read and write data between the processor
bus and the I/O bus is shown in Figure 1.  This flow allows for both
buses to simultaneously transfer read and write data at the cost of
having four ALIGN MUXES and 64 ALIGN MUX selects.  The IOCC design
adopted the data flow shown in Figure 2.  The NEW ALIGN MUXES were
carefully structured in order to be able to have one set of 16 NEW
ALIGN MUX selects.  This flow still allows for both buses to
simultaneously transfer read and write data.  However, due to the
multiplexed usage of the NEW ALIGN MUXES, there is a cycle latency at
the beginning of all block transfers. Since this flow combines the
old 64 ALIGN MUX selects into 16 NEW ALIGN MUX selects, more
complexity is introduced in the NEW ALIGN MUX selects.  These NEW
ALIGN MUX selects are nontrivial and have to dynamically modify the
NEW ALIGN MUXES based on the type of I/O transfer.  However, this
increase in complexity is minor relative to the decrease in chip data...