Browse Prior Art Database

Error Correcting Code Resistant to Five Bit Packaging Errors

IP.com Disclosure Number: IPCOM000108715D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+2]

Abstract

Disclosed is an error correcting coding scheme that detects 5-bit package errors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Error Correcting Code Resistant to Five Bit Packaging Errors

       Disclosed is an error correcting coding scheme that
detects 5-bit package errors.

      In machines which require high speed parallel busses, dense
wiring is required to reduce transmission delays. This in turn
requires that multiple driver/receiver functions be contained in a
single package.

      When the driver/receiver modules are packaged in five bits per
module, the error detection mechanism must be able to detect failures
in the package that affect all contained driver/receiver functions.
A (72,64) SEC-DED (single error correcting - double error detecting)
code capable of detecting all single 5-bit package errors is
specified by the following parity check matrix.
  The first 50 columns:

                            (Image Omitted)

      Note that this is not an odd-weight-column code. Uncorrectable
errors (UEs) are generated whenever a non-zero error syndrome does
not match any of the columns of the H-matrix.