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High Speed BiCMOS NOR Decoder/ Driver

IP.com Disclosure Number: IPCOM000108721D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Bonges, HA: AUTHOR [+2]

Abstract

A BiCMOS NOR gate is described that realizes full rail-to-rail output voltage swing without dissipating DC power. A five-input NOR is illustrated, but the concept will accommodate either fewer or more inputs. Rail-to-rail output is the result of a bootstrapped output stage. A noise suppressor is included to diminish NOR decoder noise spikes at the output. Circuit delay is appreciably less than that of a comparable CMOS equivalent function, and the circuit maintains its performance at reduced supply voltages.

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This is the abbreviated version, containing approximately 52% of the total text.

High Speed BiCMOS NOR Decoder/ Driver

       A BiCMOS NOR gate is described that realizes full
rail-to-rail output voltage swing without dissipating DC power. A
five-input NOR is illustrated, but the concept will accommodate
either fewer or more inputs.  Rail-to-rail output is the result of a
bootstrapped output stage.  A noise suppressor is included to
diminish NOR decoder noise spikes at the output.  Circuit delay is
appreciably less than that of a comparable CMOS equivalent function,
and the circuit maintains its performance at reduced supply voltages.

      The five-input BiCMOS NOR gate shown in the figure has three
main circuit functions: (1) NOR decoder, (2) Darlington output stage,
and (3) noise suppressor.  The NOR decoder consists primarily of NFET
transistors Q11, Q3, Q4, Q5 and Q6.  The NOR decoder output is
coupled to the Darlington output stage comprised of bipolar NPN
devices Q0 and QD.  Noise suppressor QZ quenches noise spikes
generated by simultaneous switching of devices in the NOR decoder.
The circuit is enabled only when clocked input IN0 is high so that
there is no DC power dissipation.

      The circuit has three modes of operation: (1) STANDBY, (2)
SELECT, and (3) NON-SELECT.
   STANDBY Mode:
   The circuit is in the STANDBY mode when IN0 is low and all other
inputs are high. The output is low, and there is no path for DC
current.
   SELECT Mode:
   The SELECT mode occurs when IN0 goes to a high logic level first,
followed by IN1-IN4 going to a low logic level. PFET Q2 turns o...