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Single Ended Receiver with Orthogonal Only Outputs

IP.com Disclosure Number: IPCOM000108723D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+2]

Abstract

The receiver circuit described assures valid complementary outputs during the sampling interval for any signal level applied to the single-ended receiver input. Valid, orthogonal outputs occur when the two outputs are always opposite logic levels during the sampling interval. Invalid, non-orthogonal outputs occur when both outputs are at the same logic level during the sampling interval. Such a receiver is particularly well-suited as a single-ended-to-differential input signal converter for error correction code (ECC) systems. ECC systems using differential logic with orthogonal inputs are capable of correcting single-bit errors even when the errors are generated by the receiver.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single Ended Receiver with Orthogonal Only Outputs

       The receiver circuit described assures valid
complementary outputs during the sampling interval for any signal
level applied to the single-ended receiver input.  Valid, orthogonal
outputs occur when the two outputs are always opposite logic levels
during the sampling interval.  Invalid, non-orthogonal outputs occur
when both outputs are at the same logic level during the sampling
interval.  Such a receiver is particularly well-suited as a
single-ended-to-differential input signal converter for error
correction code (ECC) systems.  ECC systems using differential logic
with orthogonal inputs are capable of correcting single-bit errors
even when the errors are generated by the receiver.

      The receiver circuit is shown in Fig. 1.  A single-ended input
data signal DL is precharged to Vdd by T11, which is gated by input
ARN.  See the timing relationships in Fig. 2.  Pass gates T10 and T21
have been enabled by sampling inputs S and SN so that the input data
passes directly to node 1 at the gates of clocked inverter T9/T16.
When input DL is valid, strobe signal PCR enables inverter T9/T16 via
T19 so that node 2 provides complemented data to clocked inverter
T8/T18.  When sampling input S goes high, it enables the T8/T18
inverter via T20, creating a latch that captures the data present at
that instant. Simultaneously pass gates T10 and T21 are shut off and
restore devices T5 and T6 shut off.

      Prior to...