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TTL Receiver using VT Compensated Biasing

IP.com Disclosure Number: IPCOM000108725D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Lewis, S: AUTHOR

Abstract

By running a single wire from a conventional, three-diode biasing network to all CMOS receiver circuits on a chip, chip, more noise on input voltage levels is tolerated.

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TTL Receiver using VT Compensated Biasing

       By running a single wire from a conventional, three-diode
biasing network to all CMOS receiver circuits on a chip, chip, more
noise on input voltage levels is tolerated.

      Referring to the figure, receivers on a chip are comprised of
devices P4, P5, and N1 plus inverters I1 and I2.  Devices P4, P5, and
N1 are all extra long to minimize threshold (Vt) variation.  Widths
are made small to minimize load on the one biasing circuit per chip
which is connected to receivers at node 2 of a differential amplifier
circuit comprised of devices P6, P7, N2, N3, N4, P8 and capacitor C.
A biasing network comprised of three-diode stack P1, P2, and P3
creates a bias voltage at node 1 which is used as a reference to
control the voltage at node 2.  Usually, the diode stack is a poor
power supply because process tolerance on diode thresholds results in
poorer voltage control than is found in Vdd coming into the chip.  In
this case, however, the variation in thresholds is matched between
the supply and the P5 receiver.  In practice, controlling the source
voltage of transistor P4 has the advantage of reducing amplitude of
noise from two sources, power supply variation and P device threshold
variation.