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Single Ended Tri-state Receiver for DCVS Logic

IP.com Disclosure Number: IPCOM000108727D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+3]

Abstract

By means of a precharge true-complement (TC) generator circuit that isolates and latches received data, differential input to high speed differential cascode voltage switch (DCVS) logic is restored to ground prior to firing the logic. And, if a single-ended input level is gated into a DCVS system, it stays in that state once DCVS logic is fired. Thus, high speed operation becomes possible into DCVS logic without system crashes (glitches) in some cases, e.g., late and incorrectly sensed input signals.

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Single Ended Tri-state Receiver for DCVS Logic

       By means of a precharge true-complement (TC) generator
circuit that isolates and latches received data, differential input
to high speed differential cascode voltage switch (DCVS) logic is
restored to ground prior to firing the logic.  And, if a single-ended
input level is gated into a DCVS system, it stays in that state once
DCVS logic is fired.  Thus, high speed operation becomes possible
into DCVS logic without system crashes (glitches) in some cases,
e.g., late and incorrectly sensed input signals.

      Fig. 1 shows a receiver having data input DL and
true/complement outputs Qt and Qc.  The circuit is designed to drive
a bidirectional data bus and has tri-stated outputs controlled by
input signals S and SN.  Tri-state outputs are achieved with standard
six-device gated inverter circuits formed by transistors T13 - T20
and T4 - T11 and could be replaced with clocked totem pole inverters
which are also not novel features.  Phase ARN and PCR restore
internal nodes 1, 2, and DL to high voltage Vdd through TDLR, T22 and
T21.  The timing diagram (Fig. 2) shows the receiver coming out of
restore as phase ARN goes high.  Nodes 1 and DL are thereby left
precharged high.  Phase PCR is timed to rise after signal DL is valid
and enables a clocked inverter formed by T1, T2, and T3.  A short
delay later, phase S and SN fire and simultaneously disconnect node 1
from DL by cut off of T21 and T24, and set clocked...