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Browse Prior Art Database

Internal Instruction Frequency Monitoring

IP.com Disclosure Number: IPCOM000108751D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 148K

Publishing Venue

IBM

Related People

Burton, RWB: AUTHOR [+5]

Abstract

Disclosed is a method to gather instruction profiles with minimal perturbation to the executing program and on a very large-scale integration (VLSI) design running at a cycle time beyond the capability of traditional external counting devices. A hybrid microcode/hardware implementation is described which uses hardware to count instructions and microcode to accumulate the counts in main storage. Microcode also controls the measurement process and parameters; timeslicing, count all instructions, count individual instructions, count instruction subsets, count only instructions executing during certain processes, jobs, tasks, or states. The hardware implementation for counting instructions, pattern-matching, and subsetting reduces the perturbation to executing processes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Internal Instruction Frequency Monitoring

       Disclosed is a method to gather instruction profiles with
minimal perturbation to the executing program and on a very
large-scale integration (VLSI) design running at a cycle time beyond
the capability of traditional external counting devices.  A hybrid
microcode/hardware implementation is described which uses hardware to
count instructions and microcode to accumulate the counts in main
storage. Microcode also controls the measurement process and
parameters; timeslicing, count all instructions, count individual
instructions, count instruction subsets, count only instructions
executing during certain processes, jobs, tasks, or states.  The
hardware implementation for counting instructions, pattern-matching,
and subsetting reduces the perturbation to executing processes.  The
microcode implementation reduces hardware complexity associated with
the control and accumulate functions.  This solution builds an
instruction frequency table in main storage.

                            (Image Omitted)

      Internal pattern-matching triggering in the hardware is used to
identify the instruction which is a candidate to be counted.  The
figure shows a high-level view of the dataflow used to compare the
ops.

      A register would contain the pattern of the instruction to be
counted, called the opcode compare register.  This pattern would be
compared with instructions currently executing.  One compare would be
needed for each pipe in super-scalar design.  If the instruction
pattern compares with one of the instructions executing in one of the
pipes, an opcode counter is incremented.  Each time the instruction
represented by the pattern being compared on is executed, the counter
is incremented.  Optionally, a cycle counter could also be kept for
the instruction being compared.  The cycle counter would indicate the
total number of cycles the number of instructions in the opcode
counter took to execute.  The cycle counter is easier to envision in
a non-pipelined design but can also be implemented in pipelined and
super-scalar designs.  Thus, at the end of a certain period of time,
the opcode counter contains the numbers of times the instruction
represented by the pattern contained in the opcode compare register
was executed.  The optional cycle counter would contain the number of
cycles, possibly related to a certain stage of the pipe, that the
number of instructions took to execute.  The compare register could
contain "don't cares", such that opcode subsets could be compared, or
all opcodes would compare, such that the opcode counter would contain
a count of all instructions executed.  Note, the counter would have
to increment more than one per cycle for super-scalar designs. The
optional cycle counter would contain the number of cycles.  For this
case, the cycle counter divided by the opcode counter gives cycles
per instruction (CPI). Optionally, whe...