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Browse Prior Art Database

Connectivity Switch Request Mechanism Improvement

IP.com Disclosure Number: IPCOM000108782D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 165K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+5]

Abstract

Disclosed is an enhanced protocol between communication adapters and a switch, in a network of adapters interconnected by a switch, in order to use more efficiently the switch bandwidth.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Connectivity Switch Request Mechanism Improvement

       Disclosed is an enhanced protocol between communication
adapters and a switch, in a network of adapters interconnected by a
switch, in order to use more efficiently the switch bandwidth.

      The basic hardware structure considered here consists of
several adapters Ad 1 to Ad N interconnected by a switch.

      In such a structure (Fig. 1), each adapter Ad includes a memory
in which messages are stored in queues.

      For each adapter, there is a set of receive RCV and transmit
XMT queues in the memory.

      Memory organization for the Switch Interface is shown in Fig.
2.
      . The LOQ queues contain the messages to be transmitted to
another adapter (1 queue per target).
      .The MIQ queues contain the messages to be received from
another adapter (1 queue per origin).

      The same arrangement applies for the Network Interface.

      The transmission of messages from LOQs to other adapters
through the switch is done under control of the switch which operates
in a fixed burst mode using a cell size of 32 bytes of data and
8 bytes of control information.

      Transmission of a message from LOQ j of Adapter i:
      1. The xmt adapter hardware switch interface sends to the
switch a request for connection to adapter 'j', using the 8 bytes of
control information. Therefore, it sends the address 'j' with the set
bit on.
      2. The switch memorizes the request 'i' to 'j' in an N squared
matrix, N being the number of adapters.
      3. The switch scheduler runs at each burst time its algorithm
on the request matrix, trying to maximize the granted requests with
regard to fairness between adapters
      4. When the request 'i' to 'j' is granted, the switch sends to
the xmt adapter the address 'j' of its next target and to the rcv
adapter the address 'i' of its next origin.
      5. The xmt adapter 'i' sends a 32-byte packet of the message in
LOQ 'j' to the switch with routing information address 'j'.
      6. The rcv adapter 'j' enqueues the 32-byte packet in MIQ 'i'.
      7. Steps 3 to 6 repeat until message transmission completion.
      8. The xmt adapter hardware switch interface resets its request
'i' to 'j' in the switch by sending on the 8-byte control information
the address 'j' with set bit off.

      The problem with this process deals with pipelining in the
previous protocol, as shown in Fig. 3.
      - The set request and reset request information is taken into
account by the centralized scheduler three burst times after being
sent to the switch by the xmt adapter.
      - A granted request and the associated 32-byte packet
transmission are pipelined with a delay of three burst times, this
delay being utilized by the xmt adapter for fetching the 32-byte
packet in LOQs.

      Due to this double pipelined process additional grants may be
sent to the xmt adapter, dep...