Browse Prior Art Database

Fast Zero Detect Logic for Add, Subtract, Add Extended, Subtract Extended

IP.com Disclosure Number: IPCOM000108783D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Irish, JD: AUTHOR [+2]

Abstract

A method is disclosed for generating an arithmetic logic unit (ALU) output zero detect flag in such a way that it requires only one more logic level delay than the ALU data output. The zero detect logic described supports the functions: o Add o Add Extended (also called Add with Propagate) o Subtract o Subtract Extended (also called Subtract with Propagate)

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Fast Zero Detect Logic for Add, Subtract, Add Extended, Subtract Extended

       A method is disclosed for generating an arithmetic logic
unit (ALU) output zero detect flag in such a way that it requires
only one more logic level delay than the ALU data output.  The zero
detect logic described supports the functions:
o  Add
o  Add Extended (also called Add with Propagate)
o  Subtract
o  Subtract Extended (also called Subtract with Propagate)

      The zero detect function is accomplished by implementing the
following relation:
   Result = 0  for:  x+y, x+y+Ca, x-y, x-y-Bo, if
            x = y' +  Cp
    where:  x+y     represents Add (A)
            x+y+Ca  represents Add Extended (Ae)
            x-y     represents Subtract (S)
            x-y-Bo  represents Subtract Extended (Se)
            Ca = propagated Carry for x+y+Ca
            Bo = propagated Borrow for x-y-Bo
                 and is input to the ALU as  Ca
            y' =  y  for:  x-y and x-y-Bo, and
                  y  for:  x+y and x+y+Ca
            Cp =  0  for:  x-y, and
                  1  for:  x+y, and
                  Ca for:  x+y+Ca and x-y-Bo.

      The equation:  x = y' + Cp can be logically implemented by the
following block diagram:

                            (I...