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Quiescent Power Supply Current Test for CMOS Integrated Circuits using Non-Complementary Pass Gate Logic

IP.com Disclosure Number: IPCOM000108800D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 151K

Publishing Venue

IBM

Related People

Ferro, EE: AUTHOR [+2]

Abstract

Disclosed is a quiescent power supply current test for CMOS integrated circuits (ICs) that widely use non-complementary pass gate circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Quiescent Power Supply Current Test for CMOS Integrated Circuits using Non-Complementary Pass Gate Logic

       Disclosed is a quiescent power supply current test for
CMOS integrated circuits (ICs) that widely use non-complementary pass
gate circuits.

      Fully complementary CMOS ICs consume microwatts of power when
idle.  When quiescent power supply current, IDDQ, is measured on
fully complementary CMOS ICs, currents exceeding a few hundred
microamps provide a clear indication of defects, design errors, or
other failure mechanisms.  These tests are sensitive enough to detect
single stuck- at or stuck-open faults.

      Until now, IDDQ tests required either fully complementary CMOS
circuits or additional devices and test control on non-complementary
circuits such as ratioed grounded p channel circuits.  Even pass gate
circuits had to be fully complementary when their usage was
prevalent.

      Because of the basic differences in device count, this final
restriction meant widely used pass gate circuits like multiplexers
and XOR gates required more silicon area.  Fig. 1 depicts both a
complementary and non-complementary 2:1 pass gate multiplexer (Mux).
The complementary circuit requires six devices.  The
non-complementary circuit requires only two.

      The disclosed test method does not require fully complementary
pass gate circuits when pass gate circuits are widely used.  The
increased test coverage provided by an IDDQ test is not obtained at
the expense of extra devices and larger circuits.

      Non-complementary pass gate circuits increase quiescent power
supply current because they attenuate their own output.  When a
logical one is propagated through an NFET pass gate, the rising
output turns the NFET off and the output never reaches the full Vdd
potential.  It asymptotically approaches Vdd-Vtn, where Vtn is the
NFET device threshold.  Similarly, when a logical zero is propagated
through a PFET pass gate, the falling output turns the PFET off and
the output never reaches full ground potential.  It asymptotically
approaches Gnd + Vtp, where Vtp is the PFET device threshold.

      When presented with these attenuated input levels, the next
circuit in the path conducts subthreshold current between Vdd and
ground.  This concept is depicted in Fig. 2 for a non-complementary
2:1 pass gate Mux driving an inverter.  Figs. 2(a) and 2(b),
respectively, show how an attenuated one and an attenuated zero
affect the next circuit being driven.

      Typical...