Browse Prior Art Database

High Performance Variable-Length Macro Instruction Decode Buffer

IP.com Disclosure Number: IPCOM000108802D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Henry, GG: AUTHOR [+3]

Abstract

Disclosed is a circuit which is used to process variable-length instructions such as found in Complex Instruction Set Computers (CISCs). The circuit is devised to support a variable number of bytes (1-8) written into an 11-byte register (Instruction Register), a variable number of bytes (1-11) read from the register for instruction decode and translation, a variable number of bytes (1-10) shifted back into the register, and rotation support for data in the unit. In addition, the circuit is devised in a way to help limit wiring congestion during circuit layout, thus reducing silicon area used for the function.

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High Performance Variable-Length Macro Instruction Decode Buffer

       Disclosed is a circuit which is used to process
variable-length instructions such as found in Complex Instruction Set
Computers (CISCs).  The circuit is devised to support a variable
number of bytes (1-8) written into an 11-byte register (Instruction
Register), a variable number of bytes (1-11) read from the register
for instruction decode and translation, a variable number of bytes
(1-10) shifted back into the register, and rotation support for data
in the unit.  In addition, the circuit is devised in a way to help
limit wiring congestion during circuit layout, thus reducing silicon
area used for the function.

      The figure shows DATA 0 and DATA 1 buses feeding two 4-byte
rotate multiplexers which in turn feed the data in the unit for load
operations and the 11-byte Instruction Register.  The DATA 0 and DATA
1 buses are fed from  a memory subsystem employing a mixed
instruction and data cache.  The byte rotation function performed by
the byte rotators is required for load operation less than 4-bytes
and/or misaligned (not on a 4 byte boundary) operations. The byte
rotation function is also used in concert with the three ports of the
Instruction Register for shifting data into the 11-byte Instruction
Register.  The shift amount for the instruction coming into the
Instruction Register is a function of the current number valid
instruction byte in the register, the address of the next by...