Browse Prior Art Database

MICRO Channel Slave Ready Generation During Bus Master DMA Transfers

IP.com Disclosure Number: IPCOM000108804D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

This article describes a structure to allow MICRO CHANNEL* slaves to easily implement card READY logic in order to pace Bus Masters during certain operations. The IBM RISC System/6000* (RS/6000) Input/Ouput Channel Controller (IOCC) used this method to minimize logic, meet critical MICRO CHANNEL timings and provide optimal MICRO CHANNEL compatibility for a broad range of Bus Master designs.

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MICRO Channel Slave Ready Generation During Bus Master DMA Transfers

       This article describes a structure to allow MICRO
CHANNEL* slaves to easily implement card READY logic in order to pace
Bus Masters during certain operations.  The IBM RISC System/6000*
(RS/6000) Input/Ouput Channel Controller (IOCC) used this method to
minimize logic, meet critical MICRO CHANNEL timings and provide
optimal MICRO CHANNEL compatibility for a broad range of Bus Master
designs.

      During Bus Master DMA, the RS/6000 IOCC acts as a MICRO CHANNEL
memory slave for transfers with system memory.  The IOCC caches DMA
data to reduce memory access time seen by an adapter.  To maintain
the cache, the IOCC inserts wait states via the Micro Channel
mechanism of +CD CHRDY.  When deactivated (low) by the slave, wait
states are inserted until reactivation (high).  The design challenge
included tight timings and fault tolerance as well as the standard
requirements of minimum logic and optimal MICRO CHANNEL
compatibility, since this is a system unit and could be exposed to a
myriad of adapter design points.  An additional, unique criteria was
the generation of a general design that was usable by most MICRO
CHANNEL slaves.  This was required to validate Micro Channel timings
to ensure ease of implementation for all bus participants.  The
structure in the figure provides the following features:
      1) Optimal Delay Characteristics
      - Deactivation of +CD CHRDY via -S0...