Browse Prior Art Database

Fixed Point/ Floating Point Synchronization

IP.com Disclosure Number: IPCOM000108815D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 109K

Publishing Venue

IBM

Related People

Balser, DM: AUTHOR [+2]

Abstract

This is a description of how the processor used in the RS/6000 Model 220 accomplished coordinating and controlling instruction execution in fixed-point and floating-point units to enable synchronization of the units when required.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fixed Point/ Floating Point Synchronization

       This is a description of how the processor used in the
RS/6000 Model 220 accomplished coordinating and controlling
instruction execution in fixed-point and floating-point units to
enable synchronization of the units when required.

      In a processor with multiple execution units it is desirable to
be able to speculatively dispatch instructions and allow them to
begin executing.  Since the dispatch and execution is speculative, a
means must be provided to either: 1) prevent the instruction from
changing the state of the machine until it is determined that the
instruction should in fact be completed, or 2) restore the machine to
its correct state if the instruction was completed and should not
have been.  This article presents a simple mechanism that has been
used to enable synchronization of execution units when necessary,
while still allowing the units to operate with a great degree of
independence.

      The method of interlocking used on earlier RS/6000 processors
allowed speculatively dispatched instructions to complete and then
backed them out if they should not have been done.  The method
implemented for the Model 220 incorporates purging of partially
completed instructions, and does not keep instructions from starting
when they could have.

      A two-bit counter is employed to keep track of how many
floating-point instructions have moved beyond the final stage of the
fixed-point pipeline but have not completed in the floating-point
unit.  The counter is incremented when an instruction that was also
sent to the floating-point unit moves beyond the final stage of the
fixed-point unit.  The counter is decremented when the floating-point
unit completes an instruction through its final stage.  If both units
are clearing floating-point instructions through their final stages
in the same cycle, the counter value will be unchanged.

      By allowing the floating-point unit to complete an instruction
only when the counter has a value greater than zero, it is prevented
from finishing an instruction that it should not have.  This means an
executed floating-point instruction will never have to be backed out,
and will eliminate the need to save the state of the machine before
completing a floating-point instruction.  The presence of the counter
allows the fixed-point unit to get as many as three floating-point
in...