Browse Prior Art Database

Interlocking of System Registers on Single Chip Power Implementation

IP.com Disclosure Number: IPCOM000108821D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Balser, DM: AUTHOR [+2]

Abstract

All system registers are not read and written in the same phase of an execution unit's pipeline. It is therefore necessary to ensure that a register is not written by an instruction before all preceding instructions that reference the register have read it. The difficulty is to develop a means to ensure apparent sequential referencing of registers using as little logic as possible, balanced against the need to halt the pipeline progression as infrequently as possible for high performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interlocking of System Registers on Single Chip Power Implementation

       All system registers are not read and written in the same
phase of an execution unit's pipeline.  It is therefore necessary to
ensure that a register is not written by an instruction before all
preceding instructions that reference the register have read it.  The
difficulty is to develop a means to ensure apparent sequential
referencing of registers using as little logic as possible, balanced
against the need to halt the pipeline progression as infrequently as
possible for high performance.

      The design of the processor used in the RS/6000 Model 220
employed three methods for interlocking system registers.  The
simplest of these was used for many of the Special Purpose Registers
(SPRs).  The registers were placed in a RAM that could only be read
or written by an on-chip co-processor.  This private RAM (PRAM) was
read and written using specific co-processor instructions, of which
only one could be executing at any given time.  To read or write a
register in the co-processor's PRAM , a request for a trap to the
co-processor was generated when the instruction reached the writeback
phase of the fixed point unit, and the contents of the designated
register were place in or taken from the fixed point virtual address
register (VAR).

      The second method used was to evaluate instructions during the
decode phase of the fixed point unit and set flag bits if the
instruction would update the Exception, Link, or Count registers.
These flag bits progressed through the pipeline with the instruction.
If an instruction in the decode phase of the pipeline required one of
these registers, the instruction would be held in that phase until
the flag bits for that register in all subsequent pipeline phases
were off, indicating that all updates to the register had occurred.

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