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Browse Prior Art Database

Generic Adapter Bus Interface State Machine

IP.com Disclosure Number: IPCOM000108840D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Liu, JT: AUTHOR

Abstract

Disclosed is a state machine design for Generic Adapter Bus master interface. It uses a truth table approach and provides general advanced functions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Generic Adapter Bus Interface State Machine

       Disclosed is a state machine design for Generic Adapter
Bus master interface. It uses a truth table approach and provides
general advanced functions.

      The truth table approach to design a state machine gives a
robust algorithm. Minimizing the number of states and the I/O signals
for each state makes the design possible for a complicated state
machine using this approach.

      The design supports (1) single and stream cycles on the Generic
Adapter Bus, (2) a wait state to meet the general application needs,
(3) software reset without destroying the current bus cycle, and (4)
Generic Adapter Bus protocol detection.  It increases throughout and
reduces operation latency.  A VHDL code implementation is given
(1,2,3).

      References
(1)  S. C. Chang, G. S. Delp, H. Meleis, R. M. Montalvo, D. Seidman,
A. Tantawy and D. A. Zumbo, "Generic High Bandwidth Adapter
Architecture," IBM Research Report RC 14466, IBM T. J. Watson
Research Center, Yorktown Heights, NY 10598 (March 1989).
(2)  G. S. Delp, "The Generic Adapter Bus - GAB, An Architectural
Specification," IBM Research Report RC 14670, IBM T. J. Watson
Research Center, Yorktown Heights, NY 10598 (June 1989).
(3)  J. T. Liu, "Generalized State Machine for Generic Adapter Bus
Master Interface," IBM Research Report RC 16106, IBM T. J. Watson
Research Center, Yorktown Heights, NY 10598 (September 1990).