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High Performance Receiver with Scannable Dynamic Latch

IP.com Disclosure Number: IPCOM000108868D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Horel, TA: AUTHOR [+2]

Abstract

Any of several standard receivers, e.g., an emitter coupled logic (ECL) receiver, having differential outputs is combined with an L1/L2 level-sensitive scan design (LSSD) latch to provide performance of boundary scan operation limited only by the receiver performance. The method allows the latch L1 output to be used for both normal and test operating modes. Bipolar to CMOS conversion is achieved without requiring additional, on-chip bipolar to CMOS true/complement generators.

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High Performance Receiver with Scannable Dynamic Latch

      Any of several standard receivers, e.g., an emitter coupled
logic (ECL) receiver, having differential outputs is combined with an
L1/L2 level-sensitive scan design (LSSD) latch to provide performance
of boundary scan operation limited only by the receiver performance.
The method allows the latch L1 output to be used for both normal and
test operating modes.  Bipolar to CMOS conversion is achieved without
requiring additional, on-chip bipolar to CMOS true/complement
generators.

      Referring to the figure, receiver 2 may be an ECL current
switch receiver having level shifted differential outputs T and C,
and inputs IN and reference voltage VR. Clock inputs A, B, and C to
L1/L2 latch 4 are used in selecting normal or scan mode.

      Clocks A and B are held at a constant low level for the normal
mode.  As clock C goes high, T and C data from receiver 2 at ECL
levels, is transmitted to latch 4 and captured to provide CMOS level
outputs at L1 and/or at inverted output L1N.  This output can be used
to drive a CMOS address decoding path.

      In test mode, clock C is held DC high.  As clock A goes high,
SI data is allowed to pass into latch 4 and as clock B goes high
L1 data gets captured in L2 and is available to a tester at output
L2.

      Disclosed anonymously.