Browse Prior Art Database

Volume Control of Plated Solder Pad Arrays

IP.com Disclosure Number: IPCOM000108914D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Graham, T: AUTHOR [+3]

Abstract

Electroplating of large area arrays of solder bumps is a cost-effective alternative to evaporation and sputtering for the fabrication of high density arrays of solder pads on chips and substrates for microelectronic and optoelectronic interconnect and assembly applications. However, due to the problems in controlling plating parameters over large areas containing a large number of solder pads, it is difficult to avoid local variations in the height and volume of the pads. One solution is to use very slow plating rates to minimize these problems but one cannot eliminate them totally. Variation in solder volume is undesirable since it would result in uneven joint heights when components are assembled or, in the extreme case, lead to unjoined contacts if the variations are too large.

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Volume Control of Plated Solder Pad Arrays

       Electroplating of large area arrays of solder bumps is a
cost-effective alternative to evaporation and sputtering for the
fabrication of high density arrays of solder pads on chips and
substrates for microelectronic and optoelectronic interconnect and
assembly applications. However, due to the problems in controlling
plating parameters over large areas containing a large number of
solder pads, it is difficult to avoid local variations in the height
and volume of the pads.  One solution is to use very slow plating
rates to minimize these problems but one cannot eliminate them
totally.  Variation in solder volume is undesirable since it would
result in uneven joint heights when components are assembled or, in
the extreme case, lead to unjoined contacts if the variations are too
large. In this article, we teach a method to achieve uniform pad
height/volume in plated solder pad arrays.

      The method capitalizes on the use of dry film resist technology
commonly used in plating of such solder pad arrays and the fact that
these resist films have very uniform thickness.  The process involves
plating the solder pad arrays through lithographically created
openings in dry film resist laminated to a substrate with a
conducting plating base.  Plating can be done at conditions required
to optimize parameters, such as compositional uniformity and
throughput, but not necessarily the thickness uniformity.  The key
aspect is...