Browse Prior Art Database

Serial Channel Syncrhonizer

IP.com Disclosure Number: IPCOM000108934D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 6 page(s) / 224K

Publishing Venue

IBM

Related People

Robertson, C: AUTHOR

Abstract

Disclosed is a serial channel synchronizer (SYNC) which allows serial channels to attach to the 3090EX and run at a cycle time that is independent of the processor. The SYNC allows serial channels and the 3090EX adapter to communicate asynchronously over the channel request handler bidirectional (CRH Bidi) bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Serial Channel Syncrhonizer

       Disclosed is a serial channel synchronizer (SYNC) which
allows serial channels to attach to the 3090EX and run at a cycle
time that is independent of the processor.  The SYNC allows serial
channels and the 3090EX adapter to communicate asynchronously over
the channel request handler bidirectional (CRH Bidi) bus.

      The premise of the SYNC design is to fool the adapter and
channel hardware into thinking that they are communicating
synchronously per the channel CRH Bidi specification.  In fact, the
adapter and channel are communicating totally ASYNCHRONOUSLY through
the SYNC.  The SYNC is logically transparent to both the adapter
(ADAP) and the channel (CHAN).  For normal operation, no special
commands, responses or Bidi protocol are required by the SYNC.  All
data and most control bytes pass through the SYNC unmodified.  The
SYNC must modify bits of certain control bytes, to maintain the
integrity of the operation.

      The SYNC hardware resolves potential conflicts caused when
receiving asynchronous communications from both the adapter and
channel simultaneously.  The SYNC sequences asynchronous events in
accordance with the CRH channel Bidi protocol to make them appear
logically synchronous to both the channel and adapter.  This
sequencing is accomplished by:
      1.  passing the conflicting communications on immediately,
      2.  holding the conflicted data in abeyance (until it can be
passed on legally), or by
      3.  swallowing the event.

      Fig. 1 shows the SYNC logic divided into two parts: the ADAP/
SYNC side and the SYNC/CHAN side.  Fig. 2 details each side of the
SYNC with its own unique state machine. The ADAP/SYNC side is clocked
at the adapter rate and the SYNC/CHAN side is clocked at the channel
rate.  The two state machines communicate over an internal
ASYNCHRONOUS interface.

      All communication between the adapter and the SYNC occurs
synchronously over the ADAP/SYNC Bidi at the adapter clock rate
(cycle time).  The ADAP/SYNC side state machine executes the CRH
channel Bidi protocol emulating the channel for the adapter.

      The ADAP/SYNC side receives a signal over the Internal
Asynchronous Interface indicating the presence of a CHAN REQuest on
the SYNC/ CHAN side.  After winning the Bidi, the ADAP/SYNC State
Machine reads the appropriate SYNC/CHAN buffer gating the REQuest
sequence onto its ADAP/SYNC Bidi.

      The ADAP/SYNC state machine decodes the contents of its Bidi
register (REG) and writes its contents to a specific buffer.  Once
ready, the ADAP/SYNC state machine signals the SYNC/CHAN state
machine over the internal ASYNCHRONOUS interface.

      The ADAP/SYNC buffer elements are:  Command Array 0 (CA0) and
Command Array 1 (CA1), the Extend Command Buffer (ECB), the Advance
(ADV) REG and the Fetch Array (FA).  Each of these store specific
control or data bytes from the adapter, to be sent to the...