Browse Prior Art Database

Character Synchronization with Logging

IP.com Disclosure Number: IPCOM000108936D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Gregg, TA: AUTHOR

Abstract

Disclosed is a method of controlling a character synchronization 'window' by examination of a Loss of Sync (LOS) signal. When character synchronization is lost and reacquired, the information logged includes the number of bit positions which slipped and thus caused the LOS condition. By using a microprocessor, the circuit count is minimized, the flexibility and reliability is maximized, and enhanced error logging is possible.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Character Synchronization with Logging

       Disclosed is a method of controlling a character
synchronization 'window' by examination of a Loss of Sync (LOS)
signal.  When character synchronization is lost and reacquired, the
information logged includes the number of bit positions which slipped
and thus caused the LOS condition.  By using a microprocessor, the
circuit count is minimized, the flexibility and reliability is
maximized, and enhanced error logging is possible.

      Fig. 1 shows the data path of the character sync hardware.  The
serial bit stream is received by the RX module which drives the
deserializer.  The deserializer deserializes the bit stream into 10
bit characters.  It also includes the Skip Bit circuit which causes
the deserializer to discard 1 serial bit, thus moving the 'window'.
The 10 bit characters feed the Sync Buffer where the data is
synchronized to the channel clock.  The Sync Buffer also includes a
clock synchronizing circuit which synchronizes the Skip Bit signal
generated by the microcode (channel clocked) to the deserializer
clock.

      The 10 bit characters from the Sync Buffer feed the Decoder.
This is the 10 to 8 decoder described in U. S. Patent No. 4,486,739.
The CV (Code Violation) and K28.5 (Idle Character) outputs are the
only ones used for character sync.  These two lines feed the Char
Sync (M/N) hardware.  The Char Sync logic contains a 2-bit counter
which counts code violations and a 4-bit counter which counts valid
10 bit characters or K28.5 characters.  The outputs of these counters
are used to control the Loss of Sync latch.

      The Loss of Sync latch is an input to the IFSM (Inbound Frame
State Machine).  When the LOS line goes from inactive to active, it
causes an Event Terminator which, in turn, causes an interrupt to the
microprocessor.  The microprocessor has an I/O instruction which
allows it to read buffers in the IFSM.  The contents of these buffers
describe the type of IFSM interruption.  The microprocessor also has
an I/O instruction which is used to read the state of the LOS line.

      Finally, the microprocessor has a write instruction which it
uses to control the 10-bit character boundary.  When the
microprocessor sets a particular bit in a Control Register, a 3-cycle
pulse is generated using a pair of latches.  This pulse then feeds
clock synchronizing latches in the Sync Buffer.  The output of these
latches is the Skip Bit signal and it is synchronized to the
deserializer's R...