Browse Prior Art Database

Fairness Circuit for Subsystem Arbitration

IP.com Disclosure Number: IPCOM000108943D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Branstad, MW: AUTHOR [+2]

Abstract

A fairness circuit for subsystem arbitration using a synchronous clocking scheme is disclosed. The arbitration is done such that no wait states are required, and the fairness is based on the previous granted requester (see Fig. 1). FEATURES o Synchronous arbitration reducing the risk of asynchronous input switching problems. o Arbitration is done before acknowledgement is received. No additional time (wait states) is added to cycle. o Fairness is based on previous history of arbitration. o Expandable to any number of requesting devices sharing a single acknowledge. OPERATION

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Fairness Circuit for Subsystem Arbitration

       A fairness circuit for subsystem arbitration using a
synchronous clocking scheme is disclosed.  The arbitration is done
such that no wait states are required, and the fairness is based on
the previous granted requester (see Fig. 1).
FEATURES
o  Synchronous arbitration reducing the risk of asynchronous input
switching problems.
o  Arbitration is done before acknowledgement is received. No
additional time (wait states) is added to cycle.
o  Fairness is based on previous history of arbitration.
o  Expandable to any number of requesting devices sharing a single
acknowledge.
OPERATION

      Shown in Fig. 2 is one of the specific applications in
hardware.  This use is for interrupt arbitration.

      This arbitration scheme requires no wait states whether there
are multiple requesters or just one.  The requests for usage signals
('+  INTR REQ 1' and '+ INTR REQ 2') are internally synchronized.
The arbitration logic continues to sample every 100 nanoseconds up to
the time when the request is granted (by '- IACK' in this case).  The
previous internal request history is stored in a search results list
(SRL) (multiple SRLs for an implementation of more than 2 requesters)
and used the next time when two or more requesters contend.  The
granting signal simply gates the 'winners' request.  All external
inputs are synchronized to avoid race conditions and metastability.