Browse Prior Art Database

High Speed Protocol Controller for SONET/ATM Networks

IP.com Disclosure Number: IPCOM000108953D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 6 page(s) / 294K

Publishing Venue

IBM

Related People

Hoang, Q: AUTHOR [+5]

Abstract

The High-Speed Protocol Controller (HSPC) device allows for transmission of packets or cells of data over a transmission medium characterized as having a framed, byte-aligned format, such as one using the SONET standard. A typical application of the HSPC is shown in the figure. The HSPC will have four interfaces, two line-side and two terminal-side.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 22% of the total text.

High Speed Protocol Controller for SONET/ATM Networks

       The High-Speed Protocol Controller (HSPC) device allows
for transmission of packets or cells of data over a transmission
medium characterized as having a framed, byte-aligned format, such as
one using the SONET standard.  A typical application of the HSPC is
shown in the figure. The HSPC will have four interfaces, two
line-side and two terminal-side.

      The two line-side interfaces, receive and transmit, both work
into a byte-aligned transmission interface device at rates of at
least 19.44 Mbytes/sec.  The two terminal-side interfaces are each of
36-bit width, 32 bits of data, plus 4 bits which give packet or cell
framing (SOP - Start of Packet) and status information.

      The two terminal-side interfaces each are connected to an
external FIFO of 36 bits width, and having a depth dependent upon
overall system design.  Typically, the ends of the two FIFOs opposite
to the HSPC connection are connected to a common bus as shown in the
figure.  Data transfers between the FIFOs and a data RAM are
performed over this bus.  Bus data transfers are assumed to use a
streaming-DMA approach in which whole packets or cells are
transferred between RAM and FIFO on consecutive bus cycles, without
interruption.  The Receive and Transmit Bus Control circuits shown
perform all of the functions of interfacing between the bus and the
FIFOs, including generating and interpreting the SOP and status
signal coding.

      The HSPC will accept the designated number of bytes following
the J1 byte as the (encoded) pointer to the first byte following the
last byte of the current packet/cell.  The current packet/cell could
either have began in the preceding frame, or could start at the
beginning of this one.

      If the first byte following the end of the current packet is
all-zeros, it indicates an idle condition, and this and all
subsequent zero bytes are discarded until a non-zero byte is observed
(of Hamming weight at least two).  The first non-zero byte and the
following byte(s) together contain an (encoded) pointer to the first
byte following the end of this new packet.  The bytes at the
beginning of the frame immediately after J1 may also be zeros,
similarly indicating an idle condition.  An unrecoverable error in
decoding the packet length will result in the packet being discarded.

      The HSPC will then go into an idle condition until the start of
the next start-of-packet following the next start-of-frame, when a
new pointer will be received.

      The encoded pointer, or packet length indicator, is written
into the FIFO in the two lower-byte positions, along with the code
0100 in the 4 MSB, to indicate SOP.  As the bytes of the packet are
received, they are grouped in fourth - first byte in lowest position
- and sent to the FIFO, with the 4 MSB set to 0011 to indicate
a packet word.  As each byte is received, a down-counter, originally
set by the tw...