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Complementary Metal Oxide Semiconductor 2-to-1 Adder Circuit

IP.com Disclosure Number: IPCOM000108961D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Hilker, SA: AUTHOR

Abstract

A static complementary metal oxide semiconductor (CMOS) 2-to-1 adder building block circuit which can be used along with separate carry-lookahead and sum circuits to perform high-speed addition in a high- performance CPU is disclosed. Continued

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Complementary Metal Oxide Semiconductor 2-to-1 Adder Circuit

       A static complementary metal oxide semiconductor (CMOS)
2-to-1 adder building block circuit which can be used along with
separate carry-lookahead and sum circuits to perform high-speed
addition in a high- performance CPU is disclosed. Continued

      The static CMOS 2-to-1 adder building block circuit includes a
high-speed ripple-carry adder circuit duplicated to generate the two
sums possible for an N-bit segment assuming a carry-in of 1 and a
carry-in of 0 to the segment; these sums being generated
simultaneously and before the actual carry-in to the segment is
available.  Once the carry-in has been determined with a
carry-lookahead circuit, a sum circuit selects the correct sum for
all bits in the segment.  A number of these N-bit segment building
blocks are used to build a complete 2-to-1 adder.  The segment bit
width can be chosen so that the delay to generate the two sums
matches the delay to generate the carry-in to the segment.

      Fig. 1 shows the ripple-carry adder (RCA) circuit; single-bit
generate (G(K)), propagate (P(K)), and Exclusive-OR (X(K)) terms are
required; conventional circuits can be used for G(K)-2W AND/NAND and
P(K)-2W OR/NOR and are not shown.  The X(K) terms can be built
cheaply from the circuits for G(K) and P(K).  In order to propagate
the carry at high speed, the bit carries (C(I),C(I-1),C(I-2), etc.)
are kept in inverted form for even bits of the segment and in
non-inverted form for odd bits of the segment, allowing the
field-effect transistor (FET) configuration shown. Equations for the
even-bit and odd-bit carries are shown in Fig. 1; note that a
G(I)-P(I) input pFET stack is not required (only P(I)-FET #01) and
that a ~P(I-1)-~G(I-1...